在FPGA上實作H.264 Baseline硬體解碼電路

FPGA Implementation of an H.264 Baseline Hardware Decoder

林緯明(Wei-Ming Lin)

指導教授 ： 蔡淳仁

國立交通大學/資訊學院/資訊科學與工程研究所/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.01010

摘要

本論文主旨是在Xilinx Zynq 7020 FPGA平台上建構H.264/AVC硬體解碼器，透過AXI bus protocol，將壓縮過的H.264影像檔案從DDR SDRAM搬運到實作的硬體解碼電路進行解碼，解碼完成的影像再透過AXI bus protocol儲存回DDR SDRAM。本論文主要是將過去實驗室開發的H.264/AVC硬體解碼電路之部分模組進行擴充及修正，以支援最多五張的大解析度參考畫面預測。其中最主要的架構修改是將解碼參考畫面的儲存位置從原本的on chip memory移至DDR SDRAM，再經過burst mode 傳輸所需要資料給解碼電路進行解碼，希望在效能許可的範圍內提升所實作之硬體解碼電路的解析度限制。另外，針對H.264壓縮影像的熵解碼電路，在本研究中，我們也修正了許多過去的解碼電路不符合國際標準的地方。

關鍵字

硬體解碼電路

並列摘要

In this thesis, we present the design of an H.264/AVC Hardware Decoder IP for a Xilinx Zynq 7020 FPGA platform. The behavior of the IP is as follows. The Hardware decoder IP will read the encoded H.264/AVC bitstream data from the DDR SDRAM using the AXI bus protocol. When the decoding process is finished, the decoded video frames will be written back to the DDR SDRAM. The implementation in this thesis is based on a previous H.264 decoder IP developed in-lab. This paper fixes some architecture problem of the previous H.264/AVC Decoder IP so that our design can have at most five large resolution reference frames for inter prediction. This is achieved by moving the reference frame storage from the on-chip memory to DDR SDRAM. The new architecture removes the resolution limit of the original decoder IP with some tolerable performance degradation. In additions, we have also fixed some bugs in the entropy decoder in previous design such that the resulting decoder IP from this thesis complies with the H.264 standard better.

並列關鍵字

H.264 ； FPGA

參考文獻

[4] C.-Y. Tsai, T.-C. Chen, T.-W. Chen, and L.-G. Chen, "Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder," Proc. of 48th Midwest Symposium on Circuits and Systems, vol., no., pp.1199,1202 Vol. 2, 7-10 Aug. 2005.

[5] R. Wang, M. Li, J. Li, Y. Zhang, "High throughput and low memory access sub-pixel interpolation architecture for H.264/AVC HDTV decoder," IEEE Transactions on Consumer Electronics, vol.51, no.3, pp.1006,1013, Aug. 2005.

[6] D.-Y. Shen, T.-H. Tsai,"A 4X4-block level pipeline and bandwidth optimized motion compensation hardware design for H.264/AVC decoder," IEEE International Conference on Multimedia and Expo, 2009. ICME 2009, vol., no., pp.1106,1109, June 28 2009-July 3 2009.

[11] C. Lee, Y. Yu, "Design of a motion compensation unit for H.264 decoder using 2-dimensional circular register files,"International SoC Design Conference, 2008. ISOCC '08, vol.02, no., pp.II-109,II-112, 24-25 Nov. 2008.

[12] B. Zatt, A . Azevedo, L. Agostini, A. Susin, S. Bampi,, "Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder,"IEEE Computer Society Annual Symposium on VLSI, 2007. ISVLSI '07 , vol., no., pp.445,446, 9-11 March 2007.