變異因素低敏感性之高解析度時間數位轉換器

PVT Insensitive High-Resolution Time to Digital Converter

李霈穎(Pei-Ying Lee)

指導教授 ： 黃弘一

國立臺北大學/電機資訊學院/電機工程研究所/碩士(2012年)

摘要

本篇論文提出一低變異因素之時間數位轉換器，利用鎖相迴路(Phase Locked Loop)提供穩定的參考訊號，使解析度可達到低製程(Process)、電壓(Voltage)與溫度(Temperature)之變異，且振盪器使用8級的雙端輸入延遲元件來產生16組輸出相位訊號，並使用次迴授迴路的振盪器架構來提升參考訊號的頻率，以提高時間數位轉換器的時間解析度，此外使用改善後之振盪器延遲元件與Replica偏壓電路可提高振盪器KVCO之線性度；最後藉由本論文提出的對稱型時間放大控制電路，使輸出脈波寬度與輸入的週期時間能夠相同,且可隨著放大倍率增加使解析度更加提高，做到最小之解析度為4.73ps，最大可偵測時間為57.2ns。本論文以台積電0.18um 1P6M製程實現，電路核心面積為0.77×0.32mm2，功率消耗為120mW。

關鍵字

時間數位轉換器 ； 時間放大 ； 鎖相迴路 ； 電壓控制振盪器

並列摘要

In this paper, a PVT Insensitive Time to Digital Converter is proposed to provide a stable reference clock signal of a phase-locked loop. The time resolution can be independent on process, voltage and temperature variations. In order to produce 16-phase signals, eight series of differential delay elements are utilized, then, interpolated architecture is used to increase the reference frequency such that the time resolution of the time digital converter is improved. Furthermore, implementing a delay element in the oscillator and replica bias circuit can enhance the linearity of the KVCO. Finally, this paper makes use of a symmetric time-amplify control circuit, hence, the output pulse width and input cycle time can be synchronized. As the amplification increases the resolution increases, achieving the best resolution of 4.73ps and a maximum detection time of 57.2ns. The test chip is implemented with TSMC 0.18um 1P6M process. The chip area is 0.77×0.32mm2 and the power consumption is 120mW.

並列關鍵字

TDC ； Time Amplifier ； PLL ； VCO, Interpolation

參考文獻

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