使用類比可程式化零點頻 率及預先增強器之低壓差動傳輸器

Programmable Analog Zero Equalization and Pre-Emphasis Based LVDS Transceiver for MDDI PHY

吉爾柏(Gilbert A. E. Matig-a)

指導教授 ： 黃弘一 ； 黃弘一

國立臺北大學/電機資訊學院/電機工程研究所/碩士(2010年)

摘要

無資料

關鍵字

接收器 ； 傳送器

並列摘要

This work presents the pre-emphasis, equalization and the CMFB scheme for the LVDS transmitter and receiver. The pre emphasis scheme is applied in the LVDS transmitter. It is a modified scheme wherein it tends to lower the dynamic power consumption but still is able to achieve the same amount of improvement as compared to a conventional pre emphasis scheme. The equalization scheme is applied on the LVDS receiver. This scheme utilizes programmable analog zeroes wherein such scheme allows the ability of the receiver system to reshape the frequency response of a transmission path system to a form conducive for transmission. Both pre emphasis and equalization are made programmable since it will soon be applied to a full MDDI transceiver system wherein it includes the logical blocks that process and determine the appropriate pre emphasis and equalization setting for a particular transmission path characteristic. The CMFB scheme is a technique introduced in the LVDS transmitter system wherein it enables the non-usage of area consuming passive resistor and capacitor for close loop stability compensation. The test chip is implemented using 0.18um CMOS process.

並列關鍵字

Equalization ； Pre-Emphasis ； LVDS ； MDDI PHY ； Transmitter ； Receiver

參考文獻

[1] VESA Mobile Display Digital Interface Standard, version 1, July 23, 2004.

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[5] V. Bratov, J. Binkley, V. Katzman, and J. Chroma, “Architecture and implementation of a low-power LVDS output buffer for high-speed applications,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 53, no. 10, pp. 2101-2108, Oct. 2005.

[6] S. Jamasb et al., “A 622Mhz stand-alone LVDS driver pad in 0.18um CMOS,” in Proc. IEEE Midwest Calif. Circuits and Systems (MWSCAS), vol. 2, pp. 610-613, 2001.