以0.13um CMOS 製程實現非同步式雙模降壓轉換器設計

Asynchronous Dual-Mode Buck Converter Design in 0.13 μm CMOS process

傑夫(Jefferson Abelo Hora 傑夫)

指導教授 ： 劉萬榮

國立臺北大學/電機資訊學院/電機工程研究所/碩士(2009年)

摘要

無資料

關鍵字

同步降壓轉換

並列摘要

An asynchronous architecture dual-mode DC-DC buck converter utilizing an

external Schottky diode was evaluated through HSPICE simulation in 0.13μm CMOS

process parameters and implemented using SMIC 0.13μm 1P6M 3.3/2.5V Logic

CMOS technology. This paper aimed to employ a simple, low cost, and small solution

size on-chip compensation implementation without compromising high efficiency

requirement. Maintaining high efficiency is achieved by adopting a switch-mode pulse-

width modulation (PWM) and pulse-frequency modulation (PFM) control schemes for

heavy load and light load, respectively. The main principle is to apply the mechanism

of feedback-loop theory to fix the output voltage at the desired value regardless of the

load current. Other features for this design include a proposed simple internal circuit

structure for over-temperature (OTP) and over-voltage protection (OVP), and a soft-

start operation to suppress the power-on inrush current and there is cessation of OTP

and OVP.

This converter can operate at internally fixed 1.5 MHz and variable-frequency

in PWM and PFM mode, respectively, with input voltage from 2.0 V to 3.6 V suitable

for two dry battery-powered applications. It also offers a low output ripple voltage at

about 9.5mV and 31mV in PWM and PFM mode, respectively, and a fast transient

response when the load is suddenly changed. A low output voltage is easily supported

with 0.5 V feedback voltage reference. An overall peak efficiency of about 93.9 % and

83.93 % at Vout of 1.8V and 1.2V, respectively.

並列關鍵字

Asynchronous Buck ； PWM ； PFM ； OVP ； OTP

參考文獻

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