將MOS-HBT-NDR電路應用在數位與類比電路之研究

Investigation of Digital and Analog Applications Using the MOS-HBT-NDR Circuit

劉士豪(Shih-Hao Liu)

指導教授 ： 甘廣宙

崑山科技大學/工程學院/電子工程研究所/碩士(2008年)

摘要

傳統的負微分電阻元件(negative differential resistance, NDR)是以III-V族化合物半導體製作而成，如砷化鎵(GaAs)、磷化銦(InP)材料製作，其材料有高電子移動率等優點，但不易與其它元件或電路作整合。
在本論文中，我們已經成功利用MOS與HBT的組合來設計負微分電阻電路，我們稱此負微分電阻電路為MOS-HBT-NDR電路。藉由適當設計MOS元件的寬度與長度參數(width / length)，並控制其雙端電源電壓的大小，我們可得到不同的峰值(peak)與谷值(valley)的電流-電壓特性曲線。與傳統負微分電阻元件，例如：共振穿透二極體(RTD)相比較，具有較佳電流-電壓特性曲線的調變性，對於其應用電路的設計與開發，深具研究價值。且最大的優點為可與目前國家晶片系統設計中心(CIC)所提供的CMOS製程或BiCMOS製程相配合，並可與相關元件與應用電路相整合於同一晶片上，達到積體電路化(IC)與系統晶片化(SoC)的目標。
我們已利用負微分電阻電路設計出多功能邏輯閘電路、細胞式類神經網路(CNN)電路、新型邏輯閘電路與串並聯多峰值負微分電阻電路的應用。本論文中使用國家晶片系統設計中心(CIC)提供的TSMC SiGe 0.35μm 3P3M製程製作晶片，並針對此晶片做一系列的研究與探討。

關鍵字

負微分電阻電路 ； 多功能邏輯閘電路 ； 細胞式類神經網路 ； MOBILE ； 倍頻器電路

並列摘要

The conventional negative differential resistance (NDR) is fabricated by III-V compound materials, such as GaAs and InP, with the advantage of high electron mobility. However, it is not easy to integrate with other devices and circuits.
In this thesis, we have successfully utilized the combination of MOS and HBT to design negative differential resistance circuit, which is called as MOS-HBT-NDR circuit. By designing the appropriate width and length of MOS devices and controlling the two-terminal applied voltage, we can obtain various current-voltage (I-V) characteristics with different peak and valley currents. Compared to conventional NDR devices, such as, resonant-tunneling-diode (RTD), the proposed MOS-HBT-NDR has better I-V modulation. Therefore, this MOS-HBT-NDR circuit is worthy investigating in circuit designs and applications. These applications not only could be fabricated by the CMOS or BiCMOS technique that provided by the national chip implementation center, but also it can be integrated with other devices and circuits in the same chip to achieve the goal of system on a chip (SoC).
We have utilized negative differential resistance circuits to design the multi-function logic gate circuit, cellular neural network (CNN) circuit, novel logic gate circuit and the application of cascade and parallel- connected NDR circuit.
The fabricated chip studied in this thesis is provided by the national chip implementation center, TSMC SiGe 0.35μm 3P3M process.

並列關鍵字

negative differential resistance circuit ； multi-function logic gate circuit ； cellular neural network (CNN) circuit ； MOBILE ； frequency multiplier circuit

參考文獻

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[4] K. J. Chen et al., “An exclusive-OR logic circuit based on controlled quenching of series-connected negative differential resistance devices,” IEEE Electron Device Lett., Vol. 17, 1996, pp. 309-311.

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