2.4GHz低雜訊放大器設計

2.4GHz Low noise Amplifier Design

陳皇瑋(Huang-Wei Chen)

指導教授 ： 林明權

崑山科技大學/工程學院/電子工程研究所/碩士(2004年)

摘要

本論文主要目的，在於研製有關操作於2.4GHz頻帶下低雜訊放大器之研究。論文中一共完成了3種不同結構的低雜訊放大器之設計，分別是疊接式低雜訊放大器、傳接式雙極低雜訊放大器、以及電流共用式之低雜訊放大器之研製。論文中所設計的電路均是採用TSMC 所提供之025CMOS製程，輔以由安捷倫公司所開發之射頻模擬軟體ADS (Advance Design System) 2003a與恩碩公司所開發之Ansoft Designer來進行電路的模擬與分析。
藉由模擬的方式設計了操作於2.4GHz消耗功率約為10mW左右之低雜訊放大器，其增益雜訊特性表現分別為2.6dB Noise Figures、13.3dB Small Signal Gain。2.75dB Noise Figures、19dB Small Signal Gain。2.9dB Noise Figures、20dB Small Signal Gain三顆低雜訊放大器。並且已經由實際量測得出疊接式低訊放大器的電路特性、雜訊為2.97dB，Small Signal Gain 為9.6dB，在論文中並會討論出誤差發生的原因為何。

關鍵字

低雜訊放大器 ； 電流共用式 ； 傳接式雙極 ； 疊接式

並列摘要

In this thesis, 2.4 GHz LNAs (low noise amplifiers) have been proposed and investigated. Three LNAs with different topologies including a cascode LNA, a two-stage cascade LNA, and a current reused LNA have been designed. The process used is a commercially available 0.25 mm CMOS process from TSMC, and furthermore using simulation tool, Agilent EEsof ADS (Advance Design System) 2003a and Ansoft Designer, to simulate and analyze proposed circuits.
According to simulation results of three LNAs each with about 10 mW power consumption at the center frequency of 2.4 GHz, noise figures of them are 2.6dB, 2.75 dB, and 2.9 dB, respectively, and moreover, small signal gains of them are 13.3 dB, 19 dB, and 20 dB, respectively. Additionally, measured results of noise figure and small signal gain of the proposed cascode LNA are 2.97 dB and 9.6 dB, respectively. Finally, reasons about deviations between measured results and simulation results have been discussed.

並列關鍵字

low noise amplifiers ； current reuse ； two-stage cascade ； cascode

參考文獻

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