超寬頻低雜訊放大器之設計

DESIGN OF AN ULTRAWIDEBAND CMOS LOW-NOISE AMPLIFIER

蔡安軒(An-Hsien Tsai)

指導教授 ： 黃淑絹

大同大學/電機資訊學院/通訊工程研究所/碩士(2005年)

摘要

在本論文中，我們設計一超寬頻(3.1GHz至10.6GHz)的低雜訊放大器。整體電路使用台積電 0.18μm CMOS製程參數來設計。由於其頻寬範圍極大之特性，放大器最前端的匹配電路是由一個帶通LC濾波器所構成。所設計的低雜訊放大器核心部分功率消耗僅有9mW，最大增益為6.6dB以及3.77dB的雜訊指數。低雜訊放大器的Layout佔將近1.24x0.95mm2 的面積。本論文中比較了兩種不同匹配電路對於低雜訊放大器所造成的不同影響，也將低雜訊放大器與前端所連結的天線匹配納入設計考量加以討論。低雜訊放大器電路是使用安捷倫EEsoft EDA-ADS模擬，而天線則是使用Zeland IE3D模擬。

關鍵字

低雜訊放大器、超寬頻

並列摘要

This thesis describes the design and implementation of the ultrawideband (3.1 GHz-10.6 GHz) low-noise amplifier (LNA). The circuits are designed by using TSMC 0.18μm 1P6M CMOS process. Because of the wide range of its bandwidth, the matching circuit at the front-end of the low-noise amplifier is composed by a band-pass LC filter. The designed low-noise amplifier has only 9 mW of the power dissipation at its core, with a maximum gain of 6.6 dB and 3.77 dB minimum noise figure. The layout of the LNA occupies approximately area of 1.24x0.95mm2. Two different matching techniques have been employed in our design, and the effects to the LNA are compared. In addition, impedance matching between the ultrawideband antenna at the front stage of the low-noise amplifier is also discussed and taken into account. Simulations of the low-noise amplifier design are done by Agilent EEsoft EDA-ADS, where the antenna is simulated by Zeland IE3D.

並列關鍵字

LNA、Low Noise Amplifier、UWB、Ultrawideband

參考文獻

[2] A. Bevilacqua and A. M. Niknejad, ”An Ultrawideband CMOS Low-Noise Amplifier for 3.1—10.6-GHz Wireless Receivers,” IEEE J. Solid-State Circuits, Vol. 39, No. 12, pp. 2259 -2268, Dec. 2004.

[3] A. Ismail and A. Abidi, “A 3 to 10 GHz LNA using a wideband LC-ladder matching network,” in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 384–385.

[7] A.van der Ziel, Noise in Solid State Devices and Circuits. New York:Wiley, 1986

[8] H. A. Haus et al., “Representation of Noise in Linear Two Ports,” Proc. IRE, vol. 48, pp. 69–74, Jan. 1960.

[9] S. P. Voinigescu et al., “A Scalable High-Frequency Noise Model for Bipolar Transistors with Application Optimal Transistor Sizing for Low-Noise Amplifier Design,” IEEE J. Solid-State Circuits, vol. 32, pp. 1430–1439, Sept. 1997.