使用CML之5 Gb/s金氏碼產生器RFIC的研製

TDOA (Time Difference Of Arrival)定位系統之金氏碼產生器的工作頻率越高，則定位系統的解析度就越好，若使用常見的FPGA模擬，其速度之限制將使定位系統的解析度無法提升，無法滿足未來需求，因此只有製作晶片才能滿足高傳輸速度且輕薄短小的目的。本論文藉由MCML (MOS Cuurent Mode Logic) 高速的優勢，搭配Differential Switches的應用，而將金氏碼產生器晶片的工作速率提高到5 Gb/s。本論文內容將說明目前常用的各種高速傳輸界面，並比較其優缺點，以了解為何使用MCML作為本論文的關鍵技術；另外將說明基本Gold code的產生原理，且詳細介紹所提出的新高速傳輸Gold code架構，最後使用TSMC CMOS 1P6M 0.18um 製程來實現金氏碼產生器的晶片。設計步驟包括先使用ADS模擬得到10 Gb/s Gold code，在考量佈局及粹取寄生效應之後再使用Hspice做 post-simulation後確認Gold code可工作在5 Gb/s，其中時脈產生器部份的必v消率為144 mW、PN code核心電路必v消率為82.6 mW、量測用緩衝放大器的必v消率為28.4mW ，晶片面積為1.241 x 1.373 mm2。

關鍵字

電流模式邏輯；差動開關；金氏碼

並列摘要

The faster the Gold-code generator works, the better the resolution of the TDOA (Time Difference Of Arrival) position system is. Commonly FPGA is used in the realization of a Gold-code generator, but the restriction of the working speed of FPGA limits the resolution of the position system. To realize the Gold-code generator on a chip becomes a good solution for the future demands. This thesis reports the implementation of a Gold-code generator chip consisting of MCML (MOS Cuurent Mode Logic) and differential switches which is simulated to work up to 5 Gb/s. The present high speed interfaces are reviewed and compared at the beginning of the thesis. It is helpful for the understanding why MCML is selected in this work. Then the working principles including MCML and the Gold-code generator are introduced in detail. And finally the implementation of the 5-Gbps Gode-code generator in TSMC 0.18 μm CMOS 1P6M process is described in sequence. The design steps of the implemented Gold-code generator chip include ADS simulation up to 10 Gb/s at the beginning, and then Hspice post-simulation to confirm the chip working up to 5 Gb/s under the consideration of the parasitic effects. The simulated power consumption of the clock generator is 144 mW, the PN-code generator is 82.6 mW, and the buffer amplifier is 28.4mW. The chip size is 1.241 x 1.373 mm2.

並列關鍵字

current mode logic ； Differential switches ； Gold code

參考文獻

[1]J.M Musicer, J.Rabaey , "MOS Current Mode Logic for Low Power,Low Noise CORDIC Computation in Mixed-Signal Environments", Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on pp. 102 – 107,2000.

[2]K.M. Chu and D.L. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic," IEEE Journal Solid-State Circuits, vol. SC-22, no. 4, pp. 528-532, August, 1987

[4]Anantha P. Chandrakasan and Robert W. Broderson, “Minimizing Power Consumption in Digital CMOS Circuits,” Proceedings of the IEEE, Vol 83, No. 4, April 1995, p498-523.

[5]Paul R. Gray and Robert G. Meyer, "Analysis and Design of Analog Integrated Circuits,"John Wiley and Sons, Inc., 1993.

[6]Z.Xu and P.Shi “TDOA estimation algorithm for cyclostationary signals in multipath environments” , Electronic Letters 6th ,March 2003.

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使用CML之5 Gb/s金氏碼產生器RFIC的研製

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