軟硬體共同設計演算法實現高面積效率的數位處理器

Hardware/Software Co-Design FPGA-based Digital Signal Processor with High Area Efficiency

蔡玉凱(Yu-Kai Tsai)

指導教授 ： 蔡國瑞

崑山科技大學/工程學院/電子工程研究所/碩士(2008年)

摘要

本文所完成之FPGA內嵌DSP處理器，只佔用不到Xilinx XC3S500E Spartan-3E FPGA資源的5%，因此藉由於此軟硬體共同設計的數位信號處理器，可具有高面積效率之優勢。此可重組態、可配合應用來進行指令群裁剪工作之ASIP(Application Specific Instruction Set Processor)數位信號處理器，除了適用單通道信號處理外，對於取樣頻率一致的多通道信號處理上，也能夠以分時多工軟體設計法達成多通道信號處理任務；而當多通道信號的取樣頻率不一致時，可以利用多重中斷控制器，處理多重取樣頻率的多通道信號處理問題。也因為高面積效率而可在單一的FPGA上，同時植入數個不同功能的數位濾波器或是DSP函數模組，以增加應用系統的功能效率與設計彈性；當然也可以串接模式，在單一的FPGA上同時植入數個不同功能的FIR數位濾波器，串接組成更多階的數位濾波器；因為串接的FIR數位濾波器是同時執行，可以藉由分散式處理而有效提昇系統速度。

關鍵字

數位濾波器 ； 多重中斷控制器 ； 高面積效率

並列摘要

This paper proposes a hardware/software co-design approach to reconfigure a RISC processor which is used to implement a digital filter. According to practical requirement, the application specified instruction set can be tuned, and then the processor hardware can be reconfigured to achieve higher area efficiency. With compact instruction set and single clock execution speed, the FIR design affords high speed performance for both MAC parallel procession and those HDL programs which need sequential procession.
The proposed FIR filter only consumes 5 % of Xilinx XC3S500E Spartan-3E FPGA chip area. With high area efficiency, the digital filter is not only for single channel signal processing, but also for multi-channel signal processings with same sampling frequency, which is designed by time-sharing software engineering. When the sampling frequencies of multi-channel signal are inconsistent, we can build into several different FIRs or DSP modules in a single FPGA to increase the system performance and design flexibility. Further, we can increase FIR tapping number by cascading model, or upgrading FIR sampling speed by parallel model.

並列關鍵字

DSP ； ASIP ； FPGA

參考文獻

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