使用一簡化圖形演算法之高效能數位濾波器實現

Efficient Digital-filter Implementation Using a Reduced Graph Algorithm

林佩璋(Pei-Chang Lin)

指導教授 ： 吳文榕

國立交通大學/電機學院/電機學院電信學程/碩士(2017年)

摘要

利用加法器取代乘法器的架構已在數位濾波器中所廣泛的使用。眾所周知，減少加法器個數對成本來說至關重要，除此之外，還要具有易於設計、適用性廣、靈活彈性等優點。為了解決這些問題，很多方法被提出，同時也進行了理論分析來評估其效能。本論文的目標有二，在論文的第一部分，我們考慮了各種現有的演算法作效能分析，且經過模擬，比較得出各種不同的演算法的適用情況與極限，我們改良 RAG_n 演算法以得到更廣的適用範圍及更低的成本。在論文的第二部分，我們提出一適用於混合濾波器架構的 RAG_n演算法，稱之為 混合式 RAG_n 演算法。使用低通濾波器以及均根餘弦濾波器的模擬結果顯示，我們
所改良之 RAG_n 演算法可以有較高的效率，且混合式 RAG_n 容易於設計，不需要很複雜的計算，也具有靈活調整的特性。

關鍵字

濾波器係數 ； 節省加法器 ； 加法器共用 ； 係數分組 ； 低通濾波器 ； 均根餘弦濾波器

並列摘要

A well-known method to reduce the computational complexity of a multiplier is using specially designed adders. The number of the adders is crucial to the cost of the multiplier. Despite of that, a good method must have the advantages of easy design, wide range of applications, and good flexibility. To achieve the targets, many methods have been proposed. There are two contributions in the thesis. First, we consider existing algorithms and evaluate their performance to obtain their application scenarios and limitations. Then, we modify the RAG_n algorithm to have better performance. Second, we propose a RAG_n algorithm which can be used in the hybrid architecture of the FIR filter, referred to as hybrid RAG_n algorithm. Using a lowpass filter and a SRRC filter designs, we show that the modified RAG_n algorithm has higher efficiency, and the proposed hybrid RAG_n algorithm has the advantages of easy design, low-complexity, and high flexibility.

並列關鍵字

filter coefficients ； save adders ； shared adders ； coefficient group ； Low pass filter ； SRRC filter

參考文獻

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