高遷移率鍺與先進鰭狀電晶體結構於五奈米節點金氧半場效電晶體元件之研究

Investigations of High-mobility Germanium and Advanced FinFET Structure for 5 nm Node MOSFET Devices

周承翰(Chen-Han Chou)

指導教授 ： 簡昭欣 ； 葉文冠

國立交通大學/電機學院/電子工程系所/博士(2018年)

摘要

此博士論文主要針對五奈米節點金氧半電晶體的發展做研究發表，我們於鰭狀電晶體結構與高遷移率鍺材料方面做了許多相關的研究。論文分成兩大部分做討論，第一部分為鍺元件的研究與探討，其中又分為低電阻金屬鍺化物(metal germanide)之研究與高品質鍺閘極堆疊的探討。於低電阻金屬鍺化物的研究中，我們發現了金屬鍺化物鍺化鈀(PdGe)在某些特定製程條件時會發生鈀(Pd)異常擴散進鍺基板的行為。此研究中我們做了許多實驗設計和材料分析，發現到提供過厚的鈀金屬和多晶系鍺(poly-Ge)在400度下的鍺化鈀退火製程中，過多的間隙鍺(interstitial Ge)會把在已活化在鍺晶格上的鈀原子去活化(deactivate)，而去活化的鈀會藉由間隙(interstitials)快速在鍺基板中擴散並形成基板缺陷(bulk trap)，此機制會讓PdGe/Ge蕭特基二極體產生接近歐姆效應的電流特性。此外我們利用了第一原理計算(first-principle calculations)以及計算機輔助設計(TCAD)模擬軟體解釋了這種金屬沉積的基板缺陷對蕭特基二極體造成漏電流大幅增加的行為。此異常的現象與機制的發現在目前現有的鍺化鈀相關研究中尚未被發現。另外我們提出了利用氮化鈦(TiN)金屬覆蓋於鍺化鎳(NiGe)上退火，可以有效提升鍺化鎳的熱穩定性能承受到600度的退火。我們發現可以阻擋鍺和鎳擴散的氮化鈦可以抑制鍺化鎳結塊，另外在金屬鍺化鎳和鍺(NiGe/Ge)的蕭特基介面元素分布會趨於平緩，此現象可以有效減少蕭特基介面的漏電行為。重要的是這個技術非常容易於現有技術中實現與應用。
在此論文鍺元件研究的第二部分，我們針對鍺的閘極堆疊結構做了許多電性分析與材料間反應的討論，提供了較為完整的材料觀點以及材料行為與電性表現上的關聯性，可以做為之後相關研究團隊的研究參考。此部分研究討論了金屬釔(yttrium)摻雜於氧化鍺(GeO)介面層(interfacial layer)中，對於二氧化鉿(HfO2)為基礎的閘極堆疊結構會有什麼影響。並藉由材料反應的分析結果，成功製作出超低缺陷的二氧化鉿基礎的鍺電容器以及高性能的鍺P型電晶體。另外在電性分析的部分，我們提出了一個介面缺陷能態密度萃取方法。因為傳統的電導法(conductance method)模型中只能考慮多數載子與介面缺陷的響應，故當元件操作在弱反轉區(weak inversion)時會出現少數載子響應，此時介面缺陷能態密度的取值上會出現高估的問題。因此我們提出了可以針對低能隙材料鍺萃取近似整個能隙的介面缺陷能態密度分布的方法，二能帶電導電路模型(two-band admittance circuit model)。此模型考慮了多數和少數載子與缺陷響應的等效電路模型，利用室溫下量測的電性結果就可以萃取出更準確的介面缺陷能態密度分布以及接近價帶(valence band)附近的介面缺陷能態密度。並更進一步的於此電路模型中加入了氧化層邊緣缺陷(border trap)的等效電路來分析一奈米左右介面層裡面的邊緣缺陷分布。我們發現摻雜釔在氧化鍺介面層時，可以有效降低在能量位置高於價帶0.132 eV的介面缺陷能態密度到7.0 × 1010 cm-2eV-1。我們成功利用釔摻雜的氧化鍺介面層和二氧化鉿為基礎的閘極堆疊結構製作出高等效電洞遷移率908 cm2V-1s-1的p型鍺電晶體。
在這論文的最後一部分，我們提出了一個新穎的鰭狀電晶體結構，稱之為全面式接觸T型鰭狀電晶體(contact all around T-FinFET)。此結構針對次十奈米以下的鰭狀電晶體結構提出了兩大部分的改變，一是利用製作出自我校正氧化層(self-aligned oxide)於源汲極(S/D)下面來阻擋短通道元件中的通道底部漏電流。另外利用全面式接觸(contact all around, CAA) 結構取代傳統的鑽石型源汲極應力源(source/drain stressor)來大幅降低源汲極電阻。我們利用了商業用TCAD模擬軟體來評估有機會使用於五奈米節點的元件結構並比較其電性結果。得知全面式接觸T型鰭狀電晶體可以比傳統鰭狀電晶體結構擁有更好抑制短通道效應的特性。雖然在短通道效應的抑制上還是不比閘極全環(gate all around)式結構來的有效，但是可以避免閘極全環式結構自我加熱(self-heating)的問題。因此我們認為全面式接觸T型鰭狀電晶體可以提升鰭狀電晶體結構在五奈米節點的應用機會。

關鍵字

鍺 ； 鰭狀電晶體 ； 金氧半場效電晶體 ； 金屬鍺化物 ； 計算機輔助設 ； 第一原理計算

並列摘要

In this dissertation, investigations of high-mobility germanium (Ge) and an advanced FinFET structure for 5 nm node MOSFET were proposed. The corresponding discussions can be divided into two parts. One is the development of Ge devices regarding low-resistance metal germanides and high quality gate stacks. In the part of low-resistance metal germanides, at first, a phenomenon regarding abnormal palladium (Pd) diffusion into Ge substrate occurred in certain processing conditions during palladium germanide (PdGe) formation was realized. The results of related experiments and material analyses indicated that use of thick Pd metal and insertion of a poly-Ge during an annealing of 400 C for PdGe formation can provide excess interstitial Ge. These Ge atoms would kick out the activated Pd atoms on Ge lattice sites to generate interstitial Pd in the Ge substrate. And then, interstitial Pd could fast diffuse into Ge by a direct interstitial process. This enormous Pd indiffusion probably form a great number of bulk traps, which results in an Ohmic-like PdGe/Ge Schottky diode. In addition, the first-principle calculations and technology computer-aided design (TCAD) were used to realize the mechanism regrading metal precipitation bulk traps inducing an enormous increment of junction leakage of the PdGe/Ge Schottky diode. This extraordinary phenomenon regrading Pd abnormal indiffusion has not been reported in previous PdGe related studies. Besides, we proposed using titanium nitride (TiN) metal capping on nickle germanide (NiGe) can get thermal stability enhancement of NiGe up to 600 C. The TiN, which can resist the outdiffusion of Ni and Ge, can suppress NiGe agglomeration. In addition, capping TiN on NiGe can achieve a graded element change at the NiGe/Ge interface, which results in reduction of junction leakage. Most important of all, this application of a TiN capping layer can be easily applied in present technologies.
In the second part of discussion for Ge devices in this dissertation, the various electrical analyses and discussions of material interaction associated with electrical performances for gate stacks were proposed for future Ge studies. The research related to the impact of yttrium (Y) incorporated into GeO interfacial layer (IL) on HfO2-based gate stack was discussed. Based on analytic results of material interaction, an ultra-low trap density HfO2-based Ge capacitor and a high performance Ge pFET were demonstrated successfully. Besides, we proposed a method for interface trap density (Dit) extraction. Traditional conductance method only considered the majority carrier responding with interface traps; in other words, the extraction of Dit value as the gate voltage biased at weak inversion region would be overestimated due to minority carrier response. Hence, we proposed a method for low bandgap Ge to extract the Dit distribution nearly entire Ge bandgap, namely two-band admittance circuit model. This model considers the equivalent circuit regarding majority and minority carrier responses and can be used to extract a more accurate Dit distribution by room-temperature measurement data. In addition, we further included the equivalent circuit of oxide border traps to realize the oxide border traps density (Nbt) distribution in an approximately 1 nm IL. Incorporating Y into GeO IL can achieve the Dit of 7  1010 eV-1cm-2 near E-Ev = 0.132 eV. And a high effective hole mobility of 908 cm2V-1s-1 Ge pFET was successfully fabricated by using the YGO/HfO2-based gate stack. In the last part of the dissertation, we proposed a new advanced FinFET structure, namely contact all around (CAA) T-FinFET. The structure exhibits a two parts of structure changes for the FinFET applications of sub-10-nm node. One is fabricating a self-aligned (SA) oxide beneath source/drain (S/D) region to resist the sub-channel leakage current. Another is using CAA structure to substitute for traditional diamond-shape source/drain stressor for reduction of S/D resistance. We used commercial TCAD simulation tool to evaluate various device architectures for 5 nm node devices and compared the electrical performances with CAA T-FinFET. The results indicated that CAA T-FinFET possesses better immunity of short channel effect than a traditional FinFET structure. As compared with gate all around (GAA) structure, CAA T-FinFET has less gate control ability; however, this structure can avoid the problem of self-heating effect for GAA devices. Therefore, we thought CAA T-FinFET can enhance the application opportunity of FinFET technique in the 5 nm node generation.

並列關鍵字

Germanium ； FinFET ； MOSFET ； Metal Germanide ； TCAD ； First-principle Calculations

參考文獻

References (Chapter 1)

[1-1] R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, no. 5, pp. 256–268, Jul. 1974.

[1-2] G. E. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, no. 8, pp. 114, Apr. 1965.

[1-3] M. Bohr, “The evolution of scaling from the homogeneous era to the heterogeneous era,” in IEDM Tech. Dig., pp. 1–6, Dec. 2011.

[1-4] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance,” IEEE Elec. Dev. Lett., vol. EDL-8, no. 9, pp. 410–412, Sep. 1987.