整合型扇出晶圓級封裝技術實現28 GHz低雜訊放大器應用於第五代行動通訊系統

A 28-GHz Low Noise Amplifier (LNA) Using Integrated Fan-Out (InFO) Wafer-Level Packaging Technology for 5th Generation Wireless System

彭昇楷(Sheng-Kai Peng)

指導教授 ： 吳霖堃

國立交通大學/電機學院/電信工程系所/碩士(2018年)

摘要

本論文利用扇出封裝技術整合用金屬重佈層(redistribution layer, RDL)將具有高品質因子(quality factor)的被動元件(電感、電容)與主動元件(TSMC 28nm CMOS)實現射頻前端的低雜訊放大器。為因應第五代行動通訊高速傳輸的需求，我們將此單級放大器設計在第五代行動通訊頻譜(28 GHz)，而其採用的輸入及輸出匹配網路為L型匹配，接著分別介紹低雜訊放大器的電路設計方法以及整合型扇出晶圓級封裝製程。
電路設計方面我們使用先進設計系統(Advanced Design System, ADS)進行模擬，低雜訊放大器的設計方法是要將輸入與輸出的匹配網路達到最佳的雜訊匹配點，因單層金屬重佈層的緣故匹配網路皆採用蜿蜒式電感和指叉式電容的設計。我們選用了TSMC 28 nm金氧半場效電晶體(MOSFET)，再經由高頻雜訊量測系統對其進行量測，得到電晶體的最低雜訊值、增益以及最佳gamma點，接著把量測結果建立成S參數檔案與設計的被動元件佈局(layout)進行協同模擬(co-simulation, co-sim)，可將高頻的傳輸線和寄生效應同時考慮。
製程方面我們採用的是國家奈米元件實驗室所開發的新型InFO製程，可將積體電路(Integrated circuit, IC)中佔據大量面積的被動元件實現在RDL，有效減少先進製程的尺寸，並可改善傳統球閘陣列(BGA)封裝技術所面臨接腳數目過多以及厚度過高的議題，本論文將詳細說明各道製程的原理和設計參數。

關鍵字

低雜訊放大器 ； 整合型扇出晶圓級封裝 ； 金屬重佈層

並列摘要

In this thesis, we proposed a radio frequency low-noise amplifier (LNA) implemented in Integrated Fan-Out (InFO) wafer-level packaging (WLP) technology. The high quality factor passive components and active devices (TSMC 28nm CMOS) in the LNA are fabricated using redistribution layer (RDL).
In view of the demand for high-speed transmission of 5G mobile communication, we designed this single-stage amplifier at 28 GHz which is targeted to be 5G mobile communication spectrum. The input and output of the LNA are designed with L-shaped matching networks. The circuit design method and the integrated fan-out wafer-level packaging process will be introduced separately.
In the circuit design, we used the Advanced Design System (ADS) software for simulation. The input and output matching networks of LNA are tuned to the optimal noise matching points to achieve the best performance. Because the redistribution layer is consisted of single layer of metal, we chose meander-line inductors and interdigital capacitors for our input and output matching networks. The results are measured using NDL high-frequency measurement system. Several parameters including lowest noise level, optimum Gamma (Γopt) and Gain of TSMC 28 nm MOSFET are measured. The measurement results are further established into a S-parameter file for co-simulation with passive component layout which can simultaneously take into account of high-frequency transmission line and parasitic effects.
For the technology, we used the new InFO process developed by NDL. In this case, the passive components occupying large area in integrated circuit can be realized in the RDL. It effectively reduces the size of the chip and improves the number of pins and thickness of traditional ball-grid array (BGA) packaging. In this thesis, we will introduce the principle of design and fabrication process in detail.

並列關鍵字

Low-Noise Amplifier (LNA) ； Integrated Fan-Out (InFO) ； Wafer-Level Packaging (WLP) ； Redistribution Layer (RDL) ； CMOS

參考文獻

[1] T. Wheeler, Leading Towards Next Generation "5G" Mobile Services. [Online]. Available:https://www.fcc.gov/news-events/blog/2015/08/03/leading-towards-next-generation-5g-mobile-services.

[2] Qualcomm Technology, Inc. (2017), Spectrum for 4G and 5G. [Online]. Available:

https://www.qualcomm.com/media/documents/files/spectrum-for-4g-and-5g.pdf.

[3] J. Azémar, “Fan-out and embedded die: Technology and Market,” Yole Develop. report, 2015.

[4] J. Azémer, and P. Garrou “Fan-out packaging: what can explain such a great potential?, ” Chip Scale Review Magazine, May-June 2015, pp 5-8.