本論文研製之低雜訊放大器,是使用TSMC 0.18 CMOS製程來做設計,採用電流再利用的結構並疊接於共源級放大器。此低雜訊放大器具有高增益、低雜訊且面積小的優點。第一級電路部分是使用帶通濾波器來做input matching,第二級電路,利用疊接方式使用電流再利用的架構來達到電流重複使用,以降低功率消耗。最後一節電路為一源級隨偶器,做一個電路輸出緩衝的功用,並來做output matching。供應電壓為1.8伏特,本研究的低雜訊放大器,順向增益(S21)在4-8GHz為平均為17dB,最高為20dB。逆向隔離(S12)為-30dB以下,S11為-10dB以下,S22為-10dB以下。而平均雜訊指數約為2.9dB,最低為2.7dB。
A current-reused two-stage low noise amplifier (LNA) topology is proposed, which adopts a series inter-stage resonance and optimized substrate resistance of individual transistors. The characteristics of the series inter-stage resonance with gain enhancement are compared with other alternatives. The proposed LNA is implemented based on a 0.18μm CMOS technology for 4-8 GHz WLAN. Simulation results show that the power gain is 20 dB and minimum Noise Figure (NF) is 2.7dB with the dc power supply is 1.8V.