薄膜輪廓工法之鐵電材料氧化鋯鉿負電容薄膜電晶體之製作與特性研究

Negative Capacitance and Ferroelectric Effects of FPE HZO TFTs

劉秉哲(Ping-Che Liu)

指導教授 ： 林鴻志 ； 李佩雯

國立交通大學/電機學院/電子工程系所/碩士(2019年)

摘要

本篇論文主要研究在6吋矽基板上，製造利用鐵電材料氧化鋯鉿當作閘極氧化層的背閘薄膜電晶體(使用薄膜輪廓工法來完成)，並且同時製造矽基底、矽/氮化鈦(物理濺鍍)基底與矽/氮化鈦(ALD)三種不同背閘的薄膜電晶體，分別觀察氧化鋯鉿對元件的影響。在元件製程方面，使用物理氣相沉積與物理濺鍍方式沉積完薄膜後，僅需一道光罩即可在晶圓上定義薄膜輪廓工法的圖形，完成蝕刻後即可再分別利用原子層化學氣相沉積系統、物理濺鍍與熱阻絲蒸鍍疊上閘極氧化層、通道層與金屬電極，便可完成元件。
在電性量測方面，鍍完氧化鋯鉿鐵電薄膜後皆有進行電容-電壓量測，確認氧化鋯鉿的鐵電特性。由於此元件結構採用矽基板作為共閘極(Common Gate)，因此其閘極漏電會比較大，但開關電流比(ION/IOFF)仍然可達106以上。

關鍵字

薄膜輪廓工法 ； 鐵電材料 ； 負電容 ； 薄膜電晶體

並列摘要

In this thesis, we investigate back-end-of-line (BEOL) IGZO thin-film transistors (TFTs) on 6-inch wafers with ferroelectric gate dielectric, HZO. The devices were fabricated by the film-profile engineering (FPE) scheme with common-gate configuration. To understand the impact of the gate electrode, three types of TFTs, with Si-substrate, Si/PVD-TiN, and Si/ALD-TiN as the bottom gate were fabricated. The common-gate FPE structure needs only one mask throughout the fabrication to accomplish. After the preparation of the bottom-gate material and the formation of a suspended bridge over the device center, the key FPE steps consisting of depositing HZO/Al2O3 (ALD), IGZO (Sputter) and Al (Thermal Coater) were executed to complete the device fabrication.
The C-V characteristics obtained from planar HZO capacitors for various splits generally show the effects of ferroelectricity due to the HZO. Since the HZO TFTs are in common-gate configuration with large overlap areas between the gate and source/drain, a large gate leakage is detected. However, on-off current ratio (ION/IOFF) of the HZO TFTs as high as106 can still be achieved.

並列關鍵字

Film-profile engineering ； Ferroelectric material ； Negative capacitance ； Thin film transistor

參考文獻

[1-1] R. R. Schaller, "Moore's law: past, present and future," IEEE Spectrum, vol. 34, no. 6, pp. 52-59, 1997

[1-2] S. Salahuddin and S. Datta, "Use of negative capacitance to provide voltage amplification for low power nanoscale devices," Nano Lett, vol. 8, no. 2, pp. 405-410, 2008.

[1-3] W. Y. Choi, "Comparative study of tunneling field-effect transistors and metal–oxide–semiconductor field-effect transistors," Japanese Journal of Applied Physics, vol. 49, no. 4S, p. 04DJ12, 2010.

[1-4] M. Lee et al., "Physical thickness 1. x nm ferroelectric HfZrOx negative capacitance FETs," in Electron Devices Meeting (IEDM), 2016 IEEE International, 2016, pp. 12.1. 1-12.1. 4: IEEE..

[1-5] Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices. Cambridge university press, 2013.