運用自飽和低溫削蝕與完全金屬矽化源/汲極於垂直堆疊閘極全環多晶矽無接面奈米帶電晶體之研究

A Study on Vertically Stacked Gate-All-Around Poly-Si Junctionless Nanosheet Transistors Incorporating Self-Limited Low-Temperature Trimming and Fully Silicided S/D

柯俊名(Chun-Ming Ko)

指導教授 ： 趙天生

國立交通大學/理學院/電子物理系所/碩士(2019年)

摘要

半導體微縮的目的除了在相同晶元面積上製造出更多的電晶體數目，還能提升元件性能，但也造成短通道效應與過多的漏電電流等問題。結合多晶矽(Polycrystalline Si)與無接面(Junctionless)電晶體，可以達到相對單晶矽(Monocrystalline Si)較低溫的製程溫度、簡易的製程步驟以及較輕微的短通道效應，因此非常適用於積層型三維積體電路(Monolithic 3D-ICs)。運用低溫自飽和低溫削蝕製作超薄通道，搭配閘極全環(Gate-all-around)的金屬閘極(Metal gate)與高介電氧化層(High-κ dielectric)可以提極佳的電位耦合與更低的漏電電流。垂直堆疊通道能夠在相同的元件面積下獲得更多等效通道寬度，進而提升導通電流。然而從不同層的垂直堆疊通道到源/汲極接觸的傳導路徑不一樣長，使得在同一個元件中不同通道面對著不同的串聯電阻，因此造成依位置而定的 (Position-dependent)效能。在此篇論文中，實驗數據明顯的展現出相似的特性。為了解決此問題，進一步採用完全金屬矽化(Full silicidation)製程以降低源/汲極阻值，但在過程中高溫的金屬化後退火(Post-metallization annealing)會造成次臨界效能劣化，因為金屬閘極會施加應力在高介電常數絕緣層而產生介面缺陷態(Interface states)。在同樣的退火時間下嘗試降低退火溫度後發現可以減少介面缺陷態且次臨界效效能劣化也得到改善，然而這樣的時間並不足以達成完全金屬矽化。因此退火時間與溫度需要取捨以達成最佳化的製程條件，以利同時減緩次臨界效能劣化與達成完全金屬矽化的源/汲極。

關鍵字

垂直堆疊電晶體 ； 無接面電晶體 ； 奈米帶電晶體 ； 低溫多晶矽薄膜電晶體 ； 閘極全環 ； 高介電常數材料與金屬閘極 ； 位置依賴性 ； 自飽和低溫削蝕 ； 完全金屬矽化源/汲極 ； 金屬化後退火

並列摘要

By means of device scaling, more transistors are able to be integrated in a chip and the performance will also be enhanced. However, issues like short channel effects (SCEs) and excessive leakage current emerge inevitably. With the collaboration of polycrystalline silicon and junctionless transistors, the process temperature is lower than that of monocrystalline silicon and the fabrication is more simplified; furthermore, SCEs will be suppressed. As a result, it is suitable for manufacturing monolithic 3D-ICs. In addition, incorporating self-limited low-temperature trimming to create ultra-thin channel and gate-all round metal gate with high-κ dielectric as gate oxide is able to yield excellent gate coupling and low leakage current. Vertically stacking of channels paves the way for increasing effective channel width under the same footprint; and thus boosting drive current. Nevertheless, the conduction paths to source/drain contact faced by each channel in the stack is not equal in length and therefore the series resistance is different for each channel, which is defined as position-dependent performance. In this study, the experimental results clearly exhibit such phenomenon. To resolve this problem, full silicidation is employed to further reduce the resistance of source/drain. During the high temperature post-metallization annealing, the metal gate will exert stress on high-κ dielectric, generating interface states and consequently the subthreshold characteristics are deteriorated. If the annealing temperature is lowered while annealing time stays unchanged, the interface states will be reduced and the subthreshold characteristics will be improved as well. Yet, under this condition, full silicidation is not realized according to material analysis. As a result, there is a trade-off between annealing time and annealing temperature and it takes further split testing to achieve optimization.

並列關鍵字

Vertically stacked transistor ； Junctionless transistor ； Nanosheet transistor ； Low-temperature polycrystalline silicon thin-film transistor ； Gate-all-around ； High-k and metal gate ； Position dependence ； Self-limited low-temperature trimming ； Fully silicided source/drain ； Post metalization annealing

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