一個具成本效益以最小弦波誤差為基礎應用於三角積分類比數位轉換器之內建自我測試設計

A Cost-Effective BIST Design for Delta-Sigma ADCs Based on the Sinusoidal Minimum Error Method

周勇成(Yung-Cheng Chou)

指導教授 ： 洪浩喬

國立交通大學/電機學院/電機與控制工程系所/碩士(2009年)

https://doi.org/10.6842/NCTU.2009.00851

摘要

本論文提出一個具有高成本效益之全數位內建自我測試電路，來測試三角積分類比數位轉換器之訊號對總雜訊與諧波失真比(SNDR)。我們使用了一加入數位可測性設計之二階三角積分類比數位轉換器當做待測電路。我們所提出之改進版本的全數位內建自我測試設計使用了基於弦波最小誤差(Sinusoidal Minimum Error, SME)的演算方法。在硬體實現方面，我們使用一組數位積分器來取代基準訊號產生器使得此電路較原本的設計更節省1/4左右的晶片面積，並且成功解決了因為使用積分器，而造成內建自我測試電路計算出來的雜訊與諧波失真含有額外偏移誤差的問題。除此之外，我們對於測試激發訊號產生器的位元刪減也對硬體面積的簡化做了一些貢獻。因此我們由以上的兩種方法，在不犧牲任何測試精準度或是測試頻寬的情況下完成了一個更低成本的內建自我測試電路設計。經由電路合成軟體合成結果得知：所提出的內建自我測試設計只使用了原先四分之三的晶片面積。我們並利用FPGA搭配一個數位可測性設計之二階三角積分類比數位轉換器的晶片進行量測，量測結果顯示我們的BIST設計可以測試Peak SNDR小於80dB之三角積分類比數位轉換器並且維持平均測量誤差在0.2dB以下。最後，本論文將會簡單介紹經濟部科專計畫（HOY project）研發之無線測試技術與本論文相關之聯結。所提出之全數位的內建自我測試方法配合此無線測試平台將能夠實現可攜帶式的測試平台。

關鍵字

三角積分 ； 類比數位轉換器 ； 內建自我測試 ； 弦波最小誤差 ； 成本效益 ； 數位化測試

並列摘要

In this thesis we present a cost-effective all-digital built-in-self-test (BIST) circuit design for testing the signal-to-noise and distortion ratio (SNDR) of delta-sigma ADCs. A second-order delta-sigma ADC with a design-for-digital-testability (DfDT) circuit is used as the device under test (DUT). The proposed all-digital BIST design is based on the sinusoidal minimum error (SME) method. Regard to the hardware implementation, we replaced a set of reference signal generator with a digital integrator to save about one-fourth chip area. We also addressed the issue that the BIST total-harmonic-distortions-plus-noise (THD+N) result may contain an extra offset error caused by the integrator. Besides, we truncate the signals of the stimulus generators so as to reduce the hardware overhead. With all these approaches, we achieve a low-cost BIST design without compromise of testing accuracy and testing bandwidth. The circuit synthesis results show that the proposed BIST design occupies only three-forth area of the original one. We used a FPGA board and a DfDT second-order delta-sigma ADC testchip to conduct experiments. The measurement results show that the proposed BIST design can test a delta-sigma ADC with a peak SNDR less than 80dB, and the average error between BIST results and the corresponding FFT analysis ones is less than 0.2 dB. Since this thesis is a part of project HOY founded by Ministry of Economic Affairs, we will brief how to apply the proposed BIST design to the HOY wireless test platform at the end of this thesis. It will be shown that with the proposed all-digital BIST method and the results of other subprojects, it is possible to implement a portable test platform for mixed-signal circuits.

並列關鍵字

delta-sigma ； test ； BIST ； sinusoidal minimum error ； analog to digital converter ； cost-effective ； digitally testable

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