利用雙重微影成像法製作非對稱P型金氧半場效電晶體之研究

Fabrication of Asymmetric PMOSFETs with Double-Patterning Technique

張格綸(Ke-lun Chang)

指導教授 ： 林鴻志 ； 黃調元

國立交通大學/電機學院/電子工程系所/碩士(2009年)

https://doi.org/10.6842/NCTU.2009.00955

摘要

在本篇論文，僅利用線形光學步進器並搭配雙重微影成像法可微影出0.1微米的閘極長度，這已經超越機台的微影解析度極限。利用此技巧，即使不用電子束直寫系統，仍有小於0.1微米的解析度，這對於學校的實驗研究，提供較便利的小線寬微影方法。在實驗中，雙重微影成像法在電子顯微鏡下的線寬觀測結果下，可對此方法的線寬控制精準度做檢查。雙重微影成像法並可應用在非對稱金氧半場效電晶體的結構設計，非對稱金氧半場效電晶體可以比傳統的對稱結構有所改善，傳統上為了考量製作成本以及製程上的便利性，都使用對稱的設計。而雙重微影成像法恰好可以滿足非對稱金氧半場效電晶體的智成考量。本研究調變了源極/汲極延伸區域的結構參數(接面深度)，來驗證其對於驅動電流、短通道效應的影響。實驗做出來的非對稱元件雖然有過度蝕刻造成的缺陷，但是在基本電性還有短通道效應上，仍可以分析出比對稱的結構有些許的改善。

關鍵字

非對稱 ； 雙重 ； 金氧半場效電晶體

並列摘要

In this thesis, a double patterning method using an I-line stepper has been developed to define gate length below 0.1μm, which is beyond the limit of I-line machines with standard lithographic procedure. Verifying by scanning electron microscopy (SEM), this double-patterning method has been shown to have the ability to push gate lengths to smaller than 0.1μm. This allows us to fabricate nano-scale devices without using advanced and costly lithography techniques like e-beam writer or deep-UV steppers.
Apart from the capability of forming finer line-width, double-patterning method is also feasible for design and manufacturing of asymmetric MOSFETs which have many advantages over conventional symmetric ones. The concept of implementing asymmetric source/drain (S/D) extensions is conducted in this thesis on a PMOSFET structure. The ideal MOSFET prefers a shallower drain extension junction and a deeper source extension junction, rather than the same S/D extension junction depths in the conventional symmetric ones. The basic electrical characteristics of this asymmetric PMOSFET device are examined and compared with the symmetric ones. Although an unexpected etch-induced recess phenomenon is observed, we show that many improvements are identified, especially in the enhancement of immunity to the short-channel effects.

並列關鍵字

asymmetric ； double-patterning ； PMOSFET

參考文獻

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