快閃式記憶體和金氧半電晶體元件中單一電荷所導致的可靠性議題研究

Single Charge Phenomena in Scaled Memory and CMOS Devices

馬煥淇(Huan-Chi Ma)

指導教授 ： 汪大暉

國立交通大學/電機學院/電子工程系所/博士(2011年)

https://doi.org/10.6842/NCTU.2011.00039

摘要

本篇論文主要探討在以氮化矽(SiN)為電荷儲存之快閃式記憶元件以及高介電閘極材料(high-k)金氧半電晶體元件中，單一電荷引致的可靠性議題研究。隨著高介電閘極的採用，其元件在加壓後的電流不穩定狀態之研究的重要性也逐漸增加。另外，隨著元件不斷地微縮，數顆載子散逸流失以及隨機電報雜訊(RTN)對於通道電流會造成顯著的影響，而隨機電報雜訊對浮動閘極快閃式元件操作的影響近來已廣泛地被討論，但是，隨機電報雜訊對於氮化矽快閃記憶體操作的影響只有少數論文提及，因此，本論文前半段的研究著重於氮化矽快閃記憶體中的隨機電報雜訊，在氮化矽快閃記憶體元件中，吾人基於隨機電報雜訊開發新穎一種方法來分析注入電荷的分布，並且深入討論隨機電報雜訊於浮動閘極與氮化矽快閃記憶體元件操作的不同影響之原因，接著，討論氧化鉿量子點快閃記憶體電荷流失機制，而本論文後半段，提出雙極電荷散逸模型來解釋在高介電閘極電晶體施加電壓溫度後所引致的電流轉彎實驗現象。

第一章中，說明隨著元件不斷微縮，單一載子北補捉/釋放所造成的隨機電報雜訊及少數載子散逸流失現象對元件通道電流會造成顯著的影響，並且對於隨機電報雜訊對於浮動閘極快閃記憶體操作之可靠性議題快速地回顧，另外，亦對量子點快閃記憶體材料作一精簡回顧。

第二章中，吾人研發一新穎方法來偵測小面積SONOS快閃記憶體沿著通道的表面電位變化，這個新方法是藉由結合缺陷位置萃取技術和底層二氧化矽缺陷所產生的隨機電報雜訊(Random Telegraph Noise)來達成。吾人使用這個新方法來驗證SONOS快閃記憶體中通道熱電子(Channel Hot Electron)的寫入電荷分佈和通道引發二次電子射入的電荷分佈之不同。此外，這個方法也被應用在觀察通道熱電子寫入和能帶到能帶穿隧產生之熱電洞(Band-to-Band Tunneling Hot Hole)抹除電荷分佈的不對稱現象。最後，亦利用此方法研究對於氮化矽記憶元件資料流失的機制，而我們藉由量測在寫入電子流失時電流的變化，推論出寫入電子是經由垂直方向經由底部氧化層穿遂流失。

在第三章中，我們研究了氮化矽快閃式記憶體(SONOS Flash Memory)中的寫入載子對隨機電報雜訊(Random Telegraph Noise)之振幅的影響。同時，我們對浮動閘極快閃式記憶體(Floating Gate Flash Memory)、氮化矽快閃式記憶體做了測量與模擬的工作。我們發現氮化矽記憶元件在資料寫入後隨機電報雜訊振幅分布與寫入前不同，而浮動閘極記憶元件在資料寫入前後有相同的隨機電報雜訊振幅。兩者的不同歸因於在氮化矽快閃記憶體中，隨機且分離的寫入載子造成的電流路徑滲透作用。

第四章探討高介電材料量子點快閃記憶體元件資料流失的機制。吾人分別在不同溫度下量測資料流失速度。相較於氮化矽快閃記憶體元件，高介電材料量子點快閃記憶體元件資料流失速度有強烈的溫度正相關性，無法以是適於氮化矽快閃記憶體的Frenkel-Poole激發理論解釋。吾人提出一種新的電荷流失機制：藉由熱激發穿隧機制，成功解釋其電荷流失的強烈溫度關係。

第五章中，研究高介電閘極(HfSiON) pMOSFETs在施加負電壓溫度後所導致的不穩定現象，以單電子散逸量測技術針對施加負電壓大小、量測電壓大小及施加溫度作仔細的討論，在某特定條件下，加壓後電流將從退化變化為增益模式，吾人提出雙極電荷散逸模型來解釋負電壓溫度加壓所致之汲極電流的此轉彎(turn around)現象。其原因為在不同的施加電壓溫度及量測電壓下，加壓電流的電洞與電子成分不相同所致。

最後於第六章，吾人將對本論文做個總結。

關鍵字

隨機電報雜訊 ； 氮化矽快閃式記憶元件 ； 負電壓溫度引致不穩定 ； 單電荷散逸 ； 滲透路徑 ； 電荷流失機制

並列摘要

This thesis will focus on the reliability issues of single charge phenomenon in nonvolatile flash memory device and advanced gate dielectrics CMOS device. A novel technique based on random telegraph signal (RTS) is proposed to characterize the program/erase charge profile and retention in SONOS device. Besides, the different program charge effect between floating gate (FG) and SONOS flash device is investigated. Furthermore, staircase-like post- negative bias temperature (NBT) current instability is investigated by a computer-automated measurement circuit, which minimizes the switching delay between stress and measurement.
In Chapter 1, single electron induced current fluctuation in sub-micron FETs will be introduced. First, trapping and detrapping of individual oxide defects has been readily measured in CMOS device and nonvolatile memory. Second, the phenomena of drain current steps due to individual defects in NBTI relaxation transients will be described. Also, the impact of single charge induced current variation will be pointed out. The application of nano-crystals in nonvolatile memory will be made a short introduction.
In Chapter 2, a new RTS-based method is proposed to characterize the lateral distribution of injected charge in program and erase states in a NOR-type SONOS flash memory. The concept of this method is to use RTS to extract an interface trap position in the channel and then to use the interface trap and RTS as internal probe to detect a local channel potential change resulting from injected charge during program/erase. The lateral width of the injected charge induced channel potential barrier is shown to be around 20nm in channel hot electron (CHE) program by this method. We also find that channel initiated secondary electron (CHISEL) program has a broader injected charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band tunneling erase holes is observed. The polarity of a program-state charge distribution is examined along the channel within 10-20 program/erase cycles. Nitride charge retention loss is observed by using this method.
To expound the different program charge effect between FG flash and SONOS flash, in Chapter 3, RTN in planar SONOS cells and floating-gate cells in erase state and program state are measured, respectively. We find that a SONOS cell has a wide spread in RTN amplitudes after programming while a floating gate cell has identical RTN amplitudes in erase and program states at the same read current level. A 3D atomistic simulation is performed to calculate RTN amplitudes. Our result shows that the wide spread of program-state RTN amplitudes in a SONOS cell is attributed to a current-path percolation effect caused by random discrete nitride charges.
In Chapter 4, the charge retention loss mechanism in a hafnium oxide (HfO2) dielectric dot flash memory is investigated. The temperature and time dependence of a charge loss induced gate leakage current in a large area cell are measured directly. We find that the charge loss is through a top oxide in the cell and the stored charge emission process exhibits an Arrhenius relationship with temperature, as opposed to linear temperature dependence in a SONOS flash memory. A thermally activated tunneling front model is proposed to account for the charge loss behavior in a HfO2 dot flash memory.
In Chapter 5, bipolar charge detrapping induced current instability in HfSiON gate dielectric pMOSFETs after negative bias and temperature stress is studied by using a fast transient measurement technique. Both single electron and single hole emissions are observed, leading to post-stress current degradation and recovery, respectively. The NBT stress voltage and temperature effect on post-stress current evolution is explored. Clear evidence of electron and hole trapping in NBT stress is demonstrated. A bipolar charge trapping/detrapping model and charge detrapping paths based on measured charge emission times are proposed. Finally, conclusions are made in Chapter 6.

並列關鍵字

Random Telegraph Signal ； SONOS ； NBTI ； Single charge emission ； Bipolar charge detrapping model ； Percolation path

參考文獻

Chapter 1

[1.1] C. Shen, M. F. Li, X.P. Wang, H. Y. Yu, Y. P. Feng, A. T.-L. Lim, Y. C. Yeo, D.S.H. Chan, and D. L. Kwong, “Negative U traps in HfO2 gate dielectrics and frequency dependence of dynamic BTI in MOSFETs,” IEDM Tech. Dig., pp.733-736, 2004

[1.2] S. Rangan, N. Mielke, and E. C. C. Yeh, “Universal recovery behavior of negative bias temperature instability,” IEDM Tech. Dig., pp. 341-344, 2003

[1.3] M. Denias, A. Bravaix, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, Y. Rey-Tauriac, and N. Revil, “On-the-fly characterization of NBTI in ulra-thin gate oxide pMOSFET’s,” IEDM Tech. Dig., pp.109-112, 2004

[1.5] V. Huard and M. Denias, “Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in pMOS transistors,” Proc. Int. Reliab. Phys. Symp., pp. 40-45, 2004