0.5V低功率全數位鎖相迴路設計

A 0.5V Low Power All-Digital Phase-Locked Loop

楊于昇(Yu-Sheng Yang)

指導教授 ： 蘇朝琴

國立交通大學/電機學院/電機與控制工程系所/碩士(2011年)

https://doi.org/10.6842/NCTU.2011.00200

摘要

近年來由於環保意識的抬頭，對於手持式產品而言，低功耗成為了電路設計的趨式。另外半導體的發展使得電晶體的臨界電壓有大幅的下降，但在低功耗的設計中，電源電壓下降的速度確高於電晶體臨界電壓下降的幅度。因此在低電壓操作下，電路設計勢必面臨許多問題。對鎖相迴路而言，低電壓操作造成電晶體閘極-源極間電壓減小，使得電流趨動力大幅下降，因此會限制振盪器的操作頻率。除此之外，當操作電壓下降至電晶體臨界電壓附近時，電路對於製程變異會變得非常的敏感，效能易受製程影響。在此論文中，我們提出一個使用拔靴帶式延遲單元(bootstrapped delay cell)的數位控制振盪器於全數位鎖相迴路中。由於拔靴帶式延遲單元的特性，振盪器的輸出擺幅將被放大從-VDD至2VDD。比起由傳統反向器構成的振盪器，此被放大的振幅不僅使得電晶體趨動力變強，讓振盪器能有較高速的操作，也可使振盪器延遲單元的每顆電晶體遠離次臨界區的操作，如此一來能降低對於製程變異的敏感度。最後基於這個使用拔靴帶式延遲單元的振盪器，我們實現了一個低功耗的全數位鎖相迴路，使用90奈米製程，晶片面積為0.057mm2，其操作電壓為0.5V，操作頻率範圍(locking range)為240MHz~480MHz，當輸出為400MHz時，其峰對峰值的抖動(peak-to-peak jitter)為69.1 ps，而功率消耗僅70uW 。

關鍵字

全數位鎖相迴路 ； 拔靴帶式延遲單元 ； 低功率鎖相迴路

並列摘要

In recent years, low power designs for portable devices become popular. Many consumer electronics are asked to consume as less power as possible to extend the battery lifetime. Owing to the progress in CMOS technology, the threshold voltage of the transistor keeps degrading. But the degrading of the system supply voltage is much faster. Under the low power supply environment, the gate-source voltage decreases which leads to the decay of the driving ability. Hence the operation frequency of digital circuit is limited. Besides, the system suffers from process variation badly when the supply voltage is near the threshold voltage of the transistors. For the ADPLL systems, low power supply decreases the operation frequency of the oscillator. So we propose a bootstrapped delay cell for the digitally-controlled oscillator in ADPLLs. With the bootstrapped cell, the output swing of the oscillator is –VDD to 2VDD. This enlarged swing not only enhances the driving ability but keeps the transistors operate at super VTH region. The circuit then suffers less from the process variation compared to the oscillators composed of the traditional inverters. Finally, our ADPLL is fabricated in 90nm CMOS technology. The core area is 0.057 mm2. Under supply voltage of 0.5V, the locking range is 240 MHz to 480 MHz. The peak-to-peak jitter is measured 69.1 ps while operating at 400 MHz, and the power consumption is 70uW.

並列關鍵字

ADPLL ； low power PLL ； bootstrapped delay cell ； low power ADPLL

參考文獻

[1] M. Mansuri, C. K. Yang, “A Low-Power Low-Jitter Adaptive Bandwidth PLL with Clock Buffer,” IEEE International Solid-State Circuits Conference, Feb 2003.

[2] S. Sidiropoulus et al, “Adaptive Bandwidth PLLs and DLLs Using Regulated Supply CMOS Buffers,” IEEE VLSI Symposium, 2000.

[3] M. Toyoma et al, “A Design of a Compact 2GHz-PLL with an Adaptive Active Loop Filter Circuit,” IEEE VLSI Symposium, 2003.

[4] P. Raha, “A 0.6-1.2V Low-Power Configurable PLL Architecture for 6GHz-300MHz Applications in a 90nm CMOS Process,” IEEE VLSI Symposium, pp. 232-235, Jun. 2004.

[6] Y. L. Lo, W. B. Yang, T. S. Chao, and K. S. Cheng, “Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique,” IEEE Trans. Circuits Syst. II, vol. 56, pp. no. 5, pp. 339-343, May 2009.