晶片-封裝-印刷電路板的介面設計之演算法

現今的晶片(Chip)、封裝(Package)和印刷電路板(Printed Circuit Board)，是藉由介面(Interfaces)的整合，把各自獨立的設計再加以組合成為單一個系統。隨著輸入輸出阜(Input/Output Port)的數量增加，介面也隨之變得更加複雜，然而，很少電子設計自動化工具(Electronic Design Automation tools)可以提供有效的支援。由介面所衍生的問題通常與許多設計決策(Design Decisions)有關，例如一個新產品從構思到實際推入市場所用的時間(Time-To-Market)以及生產效率；然而，這類問題的判斷不容易被公式化，因此，迫切地需要一些實際且有效的方法，推進晶片/封裝/系統的設計方便性。另一方面，在當今的設計流程中，晶片設計廠必須與封裝廠反覆地重做重新分佈層的繞線(Re-Distribution Layer Routing)，因此，從晶片設計廠的角度而言，必須與封裝廠發展協同設計、以及採用好的重新分佈層繞線器(RDL Router)，以達成快速地實現介面的目的。我們提出的晶片-封裝-印刷電路板的介面設計之演算法包含兩個部份。第一個作品是適用於繞線空間極擁擠、單層繞線無法達到100%可繞度(Routability)的情形下，採用假單層繞線概念的重新分佈層繞線器。套用於工業界的測試案例上，我們的方法可以達到100%的可繞度且同時可縮小繞線使用道的面積，表現甚至優於當今最先進的商用重新分佈層繞線器。第二個作品包含產生封裝針腳與金屬線規畫的方法，針對晶片-封裝-印刷電路板的共同設計，可避免曠費時日的繞線過程，直接產生金屬線規畫，用以估計封裝大小、信號完整性(Signal Integrity)、及可繞度分析。我們的方法可以實現晶片、封裝、系統設計的快速收斂，藉由這兩個作品，設計廠可以大幅減少設計的困難度及加快上市的時間。

關鍵字

電子設計自動化；繞線；重新分佈層；共同設計

並列摘要

Chip, package, and board are nowadays designed separately and then combined into one system by their interfaces. The interfaces have become much more complex as the number of input/output (IO) pins increases. Few commercial EDA tools provide effective support. Since the problems caused by interfaces involve many design decisions such as time-to-market (TTM) and productivity, and it is not easy to formulate, some practical and efficient interfacing methods are strongly in need to facilitate chip/package/system designs. On the other hand, iterative re-works with package houses and RDL trial routing exist in conventional design flow. Accordingly, from design houses' point of view, co-design with package houses and good RDL router must be developed to enable fast implementation of RDL. Our proposed algorithms for chip-package-board interfacing contain two parts. The first work is RDL routing on pseudo single-layer which targets at congested cases where 100\% routability cannot be achieved within single layer. Our approach can achieve 100\% routability and minimize the area for 2-layer routing on a real industrial case, outperforming a state-of-the-art commercial RDL router. The second work contains the methodologies which can generate package pin-out and wire planning for chip-package-board co-design. It provides wire planning without time-consuming routing process to estimate package size, signal integrity, and routability. Our approaches can enable fast re-spin between chip, package, and system design houses. Through these two works, design houses can greatly reduce the design efforts and time-to-market.

並列關鍵字

EDA ； ROUTING ； RDL ； CODESIGN

參考文獻

ip-chip routing for chip-package

[3] H.-C. Lee, Y.-W. Chang, and P.-W. Lee, Recent research development in

RDL Routing Algorithmz for Flip-Chip Design," in IEEE Trans. on Computer-

ip-chip design," in Proc. IEEE/ACM international Conference

on Computer-Aided Design, pp. 753- 758, Nov. 2005.

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晶片-封裝-印刷電路板的介面設計之演算法

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