具抬升式多晶矽奈米線穿隧式薄膜電晶體之研究

穿隧式場效電晶體相較於傳統金氧半場效電晶體已知具有較高的開關電流比、陡峭的次臨界擺幅以及極低漏電流。在本篇碩士論文中，我們第一次提出利用奈米線結構和抬升式源汲極來製作多晶矽穿隧式薄膜電晶體。多晶矽奈米線穿隧式薄膜電晶體的特性卻展現了較高的次臨界擺幅和較低的開關電流比。為了釐清較劣表現的原因，我們研究了不同元件在不同條件下的電流特性，例如：閘極長度、奈米線的數目、奈米線的粗細以及變溫量測，並且利用TCAD模擬探討元件的摻雜分布。透過變溫量測萃取出的活化能，我們發現這種多晶矽奈米線穿隧式薄膜電晶體的穿隧電流是由陷阱輔助穿隧效應來主導，也驗證了元件特性會較差的原因。接著將元件進行氨電漿處理，發現適中的電漿處理時間會有效降低元件中的陷阱，因此增進了關電流和次臨界擺幅。經過一系列的結果分析，這種多晶矽奈米線穿隧式薄膜電晶體會因為摻雜濃度分布的關係，沒有看到優異的電流電壓特性，或許可以透過能夠自我對準離子佈值的方法來製作奈米線穿隧式薄膜電晶體，來獲得更好的表現。

關鍵字

薄膜電晶體；多晶矽；奈米線；穿隧式電晶體

並列摘要

It has been known that tunnel field-effect transistors (TFETs) exhibit higher on/off current ratio, steep subthreshold swing, and ultralow off leakage current than conventional MOSFETs. In this study, we propose a tunnel TFT fabricated with nanowire structure and raised source/drain for the first time. The polycrystalline-silicon nanowire tunnel TFT with raised source/drain demonstrates a higher subthreshold swing, low on/off current ratio that is below our prediction. In order to clarify the cause of poor performance, we studied the I-V characteristics of devices with different conditions, such as, gate length, number of nanowires, diameter of nanowires and various temperature, and the doping profile by using the TCAD simulation. By various temperature measurements and the extracted activation energy, we found that the doping profile and the trap assisted tunneling (TAT) mainly impact the performance of poly-Si nanowire tunnel TFT. Additionally, devices were done with the NH3 plasma treatment, the moderate plasma treatment time would eliminate traps in devices, and thus the off current and the subthreshold swing were improved. From these results and analysis, we found that this kind of nanowire tunnel TFTs would not have superior I-V characteristics due to doping profile problem. To obtain better performance, nanowire tunnel TFTs might be fabricated with self-aligned implantation.

並列關鍵字

thin ； poly-Si ； nanowire ； tunnel FET

參考文獻

[1] C. H. Fa and T. T. Jew, "The poly-silicon insulated-gate field-effect transistor," Electron Devices, IEEE Transactions on, vol. 13, pp. 290-291, 1966.

[3] M. G. Clark, "Current status and future prospects of poly-Si devices," Circuits, Devices and Systems, IEE Proceedings -, vol. 141, pp. 3-8, 1994.

[4] K. J. Kuhn, "Moore's Law Past 32nm: Future Challenges in Device Scaling," in Computational Electronics, 2009. IWCE'09. 13th International Workshop on, 2009, pp. 1-6.

[6] D. Hisamoto, "Multi-gate CMOS with fin-channel structures beyond planar CMOS scaling limits," in Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on, 2004, pp. 96-99 vol.1.

[7] I. Ferain, C. A. Colinge, and J.-P. Colinge, "Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors," Nature, vol. 479, pp. 310-316, 2011.

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具抬升式多晶矽奈米線穿隧式薄膜電晶體之研究

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