金屬源極與汲極工程對磷化銦金氧半場效電晶體特性影響之研究

Investigation of the Effect of Metal S/D Engineering on the Characteristics of InP MOSFETs

唐晨揚(Chen-Yang Tang)

指導教授 ： 簡昭欣

國立交通大學/電機學院/電子工程系所/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.01021

摘要

在此篇論文中，首先，我們製作了三氧化二鋁/磷化銦基板和二氧化鉿/磷化銦基板之金氧半電容。之後，我們利用氮氣後沉積退火去探討不同退火溫度下對於金氧半電容特性之影響。此外，我們還搭配電導法去萃取金氧半電容之介面缺陷密度，對於三氧化二鋁/磷化銦金氧半電容，我們可以獲得低介面缺陷密度大約(1×1012 eV-1cm-2)，而對於二氧化鉿/磷化銦金氧半電容，在後沉積退火300度條件下，介面缺陷密度甚至可以低於(1×1012 eV-1cm-2)。除此之外，我們發現在不同後沉積退火溫度條件下的介面缺陷和平帶電壓的移動有相同的趨勢，此結果顯示介面缺陷多容易捕捉電荷使得平帶電壓產生平移。最後，我們利用XPS 分析，得知In2O3氧化態的存在，會使介面缺陷密度上升，降低氧化層介面品質。
之後，鎳磷化銦合金利用兩段式快速熱退火製作完成，在不同快速熱退火溫度條件下，其中以第一段退火溫度150度搭配第二段退火溫度250度的鎳磷化銦合金擁有最佳電性，包含低理想因子(1.4)和高開關電流比(1.76×103)，接著我們利用變溫量測去萃取此條件下的電洞蕭特基能障大約(0.76 eV)。而由XRD分析可以證明鎳磷化銦合金能利用二階段快速熱退火成功合成。接著再藉由XPS縱深分析去探討各個元素在合金中的分佈，由結果可以看出，當第二階段退火達到300度以上時，金屬銦會往表面擴散，相反地，金屬鎳則會往內部擴散，此結果相對印證在第二段退火溫度達300度以上的鎳磷化銦合金厚度會高於第二段退火溫度低於250度的厚度。
接著，利用前述的金氧半電容和鎳磷化銦蕭特基接面製作流程，我們成功地製造出磷化銦金氧半場效電晶體，此元件使用三氧化二鋁為閘極氧化層，源極和汲極區域使用二階段快速熱退火形成鎳磷化銦合金。此元件擁有高電流開關比(2.66×104)和不錯的次臨界擺幅(204 mV/dec)。我們比較不同二階段快速熱退火溫度下的元件電性，可以發現使用第二段退火溫度300度和350度的兩種元件，在導通電流方面明顯下降，之後，我們利用單一電晶體法(single transistor method)去萃取不同退火條件下的元件源極和汲極電阻，同樣發現在第二段退火300度和350度的兩種元件，其源極和汲極電阻明顯高於其他三者。由於前述XPS縱深分析提到在高溫退火下，金屬銦會往表面擴散，並且在表面有氧訊號出現，由此結果得出，元件電流下降的主因是由於金屬銦在高溫退火下往表面擴散，進而在表面形成銦的氧化物，使源極和汲極阻抗增加。
最後，為了有效降低等效氧化層厚度，我們選擇三氧化二鋁搭配二氧化鉿當作我們的閘極氧化層，同樣地，我們成功製作出磷化銦金氧半場效電晶體，一樣能獲得高電流開關比(1.27×104)和不錯的次臨界擺幅(219 mV/dec)。接著我們比較使用三氧化二鋁和使用三氧化二鋁加二氧化鉿為閘極氧化層的兩種元件特性，由於等效氧化層厚度的減少，使得最高驅動電流上升1.58倍，但相對地，等效氧化層厚度的降低，也會使閘極漏電流上升，使得電流開關比下降。

關鍵字

磷化銦 ； 金氧半場效電晶體 ； 三氧化二鋁 ； 二氧化鉿 ； 金屬源極與汲極

並列摘要

In this thesis, we firstly fabricated the Al2O3/InP and HfO2/InP MOS capacitors. Then the PDA treatment in N2 ambient was used to discuss the electrical properties of MOS capacitors with various PDA temperatures. The Dit was extracted by conductance method. For Al2O3/InP MOS capacitors, Dit was approximately of 1×1012 eV-1cm-2. On the other hand, for HfO2/InP MOS capacitors, the Dit was even lower than 1×1012 eV-1cm-2 with PDA at 300C. Besides, we found that the Dit distribution with various PDA temperatures was in connection with flat band voltage shift. It demonstrated that existed higher interface state would cause more negative flat band voltage shift. Finally, the XPS analysis revealed that the In2O3 phase would degrade oxide quality and increase Dit .
Secondly, the Ni-InP alloy was successfully formed by two-step annealing process. The Ni-InP junction of first step at 150 C with second step at 250 C exhibited good electrical performance, including low ideality factor of 1.4 and high Ion/Ioff ratio of 1.76×103. The hole Schottky barrier height of 0.76 eV was extracted by current-temperature measurement. In addition, the XRD analysis was used to prove that the Ni-InP alloy could be formed successfully by two-step annealing process. Moreover, the XPS depth profile showed the elemental distribution in the Ni-InP alloy. The In atoms diffused to surface when the second step annealing temperature over 300C. On the other hand, the Ni atoms diffused into InP bulk when the second step annealing temperature over 300 C which induced Ni-InP alloy thickness increasing.
Thirdly, the InP MOSFETs using Al2O3 as gate oxide with metal S/D were demonstrated. The S/D region was formed by two-step annealing process. The device exhibited high Ion/Ioff ratio of 2.66×104 and good subthreshold swing of 204 mV/dec. Then we compared the electrical characteristics of InP MOSFETs with various second step annealing temperatures. It revealed that the on current of the device with second step annealing at 300 and 350 C conditions degraded obviously. Because of the Ni-InP alloy XPS depth profile, we speculated that the reason of current degradation was that the In atoms diffused to the surface and formed Indium oxide which caused high resistance in S/D region. After that, the S/D resistance was extracted by single transistor method. The S/D resistance of the device with second step annealing at 300 and 350 C were higher than those of the devices subject to other three annealing conditions which was compatible as our expectation.
Finally, in order to scale down equivalent oxide thickness (EOT), we used Al2O3 accompanied with HfO2 as gate oxide. The InP MOSFETs exhibited high Ion/Ioff ratio of 1.27×104 and good subthreshold swing of 219 mV/dec. Due to the reduction in EOT, the driving current of the device using Al2O3 accompanied with HfO2 was 1.38 times higher than that using Al2O3 as gate oxide. However, the gate leakage also increased because of the EOT reduction and in turn led to the Ion/Ioff ratio degradation.

並列關鍵字

InP ； MOSFET ； Al2O3 ； HfO2 ； Metal S/D

參考文獻

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