矽奈米金氧半場效電晶體之汲極電流匹配與低頻雜訊研究及分析

Investigation and Analysis of Drain Current Mismatch and Low Frequency Noise for Nanoscale MOSFETs

郭俊延(Jyun-Yan Jack Kuo)

指導教授 ： 蘇彬

國立交通大學/電機學院/電子工程系所/博士(2011年)

https://doi.org/10.6842/NCTU.2011.01076

摘要

本論文探討先進MOSFET元件的汲極電流匹配及低頻雜訊特性。首先，關於低頻雜訊，利用單軸應力來改善元件特性已是必然趨勢，但其對低頻雜訊的影響，過去文獻研究僅著重單軸應力的製程所造成的低頻雜訊變化，我們利用有/無使用單軸應變矽的元件，分析其低頻雜訊及閘極絕緣體/半導體接面的缺陷密度，發現單軸壓縮應變矽的使用本質上會降低電洞對閘極絕緣層的波函數穿透，進而改善載子數量變動主導的低頻雜訊，但單軸壓縮應變矽的使用會惡化由載子遷移率變動主導的低頻雜訊，這是因為載子遷移率變動來自載子的聲子散射，而單軸壓縮應力會導致載子更為聲子散射。
此外，本論文廣泛研究單軸應力對汲極電流匹配在各個操作區間的影響。當元件操作在低閘極電壓時，無論是在線性區或是飽和區，單軸壓縮應變矽的使用會導致汲極電流匹配差異變大，這是因為低閘極電壓下汲極電流匹配差異主要來自於臨界電壓的匹配差異並與電導效率成正比，雖然研究發現臨界電壓的匹配差異不會受單軸壓縮應力影響，但單軸壓縮應力會增加電導效率進而使汲極電流匹配差異變大。當元件操作在高閘極電壓時，線性區的汲極電流匹配差異會因單軸壓縮應變矽的使用而變小，這是因為低閘極電壓下汲極電流匹配差異主要來自於電流因子的匹配差異，又電流因子的匹配差異與載子遷移率成反比，而載子遷移率因為單軸壓縮應力而獲得增加。在飽和區時，使用壓縮應變矽的元件其汲極電流匹配差異有更顯著的變小，這是因為此時汲極電流匹配差異部份來自臨界電壓的匹配差異並與電導效率成正比，而單軸壓縮應力會減少電導效率。針對單軸壓縮應力對汲極電流匹配的溫度效應之影響，研究指出，當元件操作在線性區高閘極電壓下，汲極電流匹配對溫度變化較不敏感，但當元件操作在飽和區時，使用壓縮應變矽的元件其高閘極電壓下的汲極電流匹配差異隨溫度的降低而變小。上述汲極電流匹配的溫度效應主要來自於載子遷移率的溫度特性，而單軸壓縮應力會造成載子遷移率對溫度更敏感。
另外，利用對稱/非對稱環形佈植元件的分析，研究發現，元件的臨界電壓匹配差異起源於環形佈植區的隨機摻雜濃度變化，又隨機摻雜濃度變化影響程度與環形佈植面積成反比，因此非對稱環形佈植元件的臨界電壓匹配差異較對稱環形佈植元件大。更重要的是，因為環形佈植區的面積與通道長度無關，因此只要有使用環形佈植，長通道元件臨界電壓匹配差異仍會相當明顯。
一直以來，SOI元件的self-heating對元件特性的影響都是重要議題，我們的研究發現， self-heating的存在即造成一個回饋效應，並且會使汲極電流匹配差異變小，針對此一回饋效應，我們提出了一個新的汲極電流匹配模型，此新模型能貼切的描述SOI元件的汲極電流匹配。我們也有研究源極/汲極串聯電阻對汲極電流匹配的影響，發現源極/汲極串聯電阻對短通道元件的電流匹配是很重要的。
針對電路應用會為了降低功耗而操作在次臨界區，我們亦對次臨界區的汲極電流匹配及其模型做深入的研究。研究發現，次臨界區的汲極電流匹配差異主要來自於臨界電壓匹配差異、次臨界擺幅匹配差異、臨界電壓匹配差異與次臨界擺幅匹配差異的相關度。其中臨界電壓的決定是相當重要的關鍵，我們發現，利用定電流方式決定的臨界電壓能取得較合理的臨界電壓匹配差異，並貼切的描述次臨界區汲極電流匹配。我們並發現，次臨界擺幅匹配差異對小尺寸元件是重要的，而臨界電壓匹配差異與次臨界擺幅匹配差異的相關度則對長通道元件是重要的。

關鍵字

金氧半場效電晶體 ； HASH(0xa5b747c) ； 單軸應變 ； HASH(0xa5b8018) ； 汲極電流匹配 ； HASH(0xa5b8108) ； 低頻雜訊

並列摘要

This dissertation investigates and analyzes the drain current mismatch and low frequency noise properties for nanoscale MOSFETs. Through a comparison of the input-referred noise and the trap density of the gate dielectric/semiconductor interface between co-processed strained and unstrained pMOSFETs, it is found that the tunneling attenuation length λ for channel carriers penetrating into the gate dielectric is reduced by uniaxial strain. This reduced λ may result in smaller carrier-number-fluctuations origin low frequency noise, which represents an intrinsic advantage of low frequency noise performance stemming from process-induced strain. On the other hand, it is found that the normalized drain current noise of the strained device in the high gate overdrive (Vgst) regime is larger than its control counterpart. In addition, the enhanced carrier-mobility-fluctuations origin 1/f noise for the strained device in the high |Vgst| regime indicates that the carrier mobility in the strained device is more phonon-limited, which represents an intrinsic strain effect on the low frequency noise.
Impact of uniaxial strain on drain current mismatch and its temperature dependence under various operation conditions are investigated systematically. With the adoption of uniaxial compressive strained silicon, drain current mismatch for the strained device in the low |Vgst| regime is enhanced while the threshold voltage mismatch of the strained device is nearly identical to that of the control one. The increased drain current mismatch for the strained device can be attributed to the enhanced gm/Id. In the high |Vgst| linear region, the smaller drain current mismatch for the strained device results from its smaller current factor mismatch σ(Δβ)/β. In the high |Vgst| saturation regime, the improvement in drain current mismatch for the strained device is further enhanced because of the strain-reduced electric field for velocity saturation (Esat).
Regarding the temperature dependence of the device mismatching properties, our result indicates that the drain current mismatch versus temperature trend for the strained device is different from the unstrained one. In the high |Vgst| linear regime, the compressively-strained device shows smaller increment in drain current mismatch than the unstrained counterpart as temperature decreases. In the high |Vgst| saturation region, opposite to the unstrained case, the drain current mismatch of the compressively-strained device decreases with temperature. The underlying mechanism is the larger temperature sensitivity of carrier mobility for the strained device.
The mismatching properties in nanoscale MOSFETs with symmetric/asymmetric halo implant are also investigated. We show that the threshold voltage mismatch is mainly determined by the RDF in the halo-implanted region, and the threshold voltage mismatch for the asymmetric device is larger than that of the symmetric one.
Impact of self-heating on drain current mismatching properties for SOI devices are investigated. It is found that self-heating induces a feedback effect and reduces the drain current mismatch. A drain current mismatch model considering the self-heating induced feedback effect is proposed. The accuracy of the new model has been verified with experimental data. This effect needs to be considered when one-to-one comparisons between SOI and bulk devices regarding the variability are made. In addition, impact of source/drain series resistance on the drain current mismatch is investigated. The impact of source/drain series resistance on the drain current mismatch will become increasingly important for devices with scaled channel length.
Since subthreshold circuits are increasingly important for low power applications, subthreshold drain current mismatch modeling is crucial. To model the subthreshold drain current mismatch more physically and accurately, our study suggests the constant-current method instead of the maximum slope method should be used for the determination of threshold voltage. Our study indicates that the subthreshold swing mismatch is important for devices with small geometries. It is also found that the correlation between the threshold voltage mismatch and the subthreshold swing mismatch needs to be considered in the subthreshold drain current mismatch modeling especially for long channel devices.

並列關鍵字

MOSFET ； HASH(0xa5b824c) ； uniaxial strain ； HASH(0xa5b8318) ； drain current mismatch ； HASH(0xa5b8c70) ； low frequency noise

參考文獻

Chapter 1

[6] L. K. J. Vandamme and F. N. Hooge, “What Do We Certainly Know About 1/f Noise MOSTs,” IEEE Trans. Electron Devices, vol. 55, no. 11, pp.3070-3085, Nov. 2008.

[7] G. Ghibaudo, T. Bouchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectron. Reliab., vol. 42, no. 4/5, pp.573-582, Apr./May 2002.

[8] Y. Tateshita et al.,” High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates,” IEDM Tech. Dig. 2006, pp.1-4.

[9] S. E. Thompson, G.Sun, Y.S. Choi, and T. Nishida, “Uniaxial-process-induced strained-Si: extending the CMOS roadmap,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp.1010-1020, May 2006.