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  • 學位論文

矽奈米線場效電晶體的雜訊研究

Numerical Study of RTN Amplitude in SiNWFETs

指導教授 : 渡邊浩志

摘要


近年來,在電晶體尺寸不斷的微縮下,最先進的半導體元件製程已經到了奈米級別。因此,傳統的金屬氧化物半導體場效電晶體(MOSFET)已經多半被鰭式場效電晶體(FINFET)取代,如果尺寸在不斷微縮下,在未來或許鰭式場效電晶體會被矽奈米線場效電晶體(SiNWFET)取代。在這種情形下,垂直於電子傳輸方向有非常大的二維量子局限效應,且介電質層缺陷(trap)也會對通道內電位影響非常大。所以在矽奈米線場效電晶體的缺陷到底會如何影響通道電流?   此篇論文的目的在於研究在矽奈米線場效電晶體的結構下,不同位置的缺陷對雜訊振幅(random telegraph noise amplitude)有何影響。我們使用自製的模擬器來模擬三維的高介電質矽奈米線場效電晶體,其中矽奈米線的截面積厚度只有三點二奈米,因此會有很強的量子局限效應。因此在本篇論文中,我們會先介紹雜訊振幅的物理模型和載子傳輸模型,其中我們使用密度梯度(density gradient)模型來模擬元件的局限效應。最後,藉由分析模擬結果,我們可以得到在強反轉層時,當通道中心的電子濃度越高,雜訊振幅明顯變低。我們也可以得到在弱反轉層時,介電質層缺陷在靠近通道中心有最大的雜訊振幅。

並列摘要


In recent years, the miniaturization of transistors has progressed according to the device scaling rule and then the geometry of the most advanced transistor reaches in the level of nano-meters. The device structure of transistor also has substantially changed from the conventional MOSFET. The plain substrate is replaced with silicon FIN to form FINFET. If the device scaling progresses further, the silicon FIN may be replaced with silicon nanowire to form SiNWFET soon. This trend decisively enhances two-dimensional confinement of electrons’ wave in channel, which is perpendicular to the direction of electrons’ transport from source to drain. On the other hand, the charge of a trapped electron in gate dielectric may significantly influence potential profile inside channel under the influence of two-dimensional confinement. If a trap is so close to the channel in SiNWFET, how may it modulate drain current flowing through channel? Or, how may it influence the amplitude of random telegraph noise (RTN) in SiNWFETs?   The goal of the present thesis is to numerically investigate how the RTN amplitude varies with the change in the location of trapped charge in SiNWFET. We use a homemade three-dimensional device simulator to simulate a high-K gate SiNWFET comprising a silicon nanowire having 3.2 nm on a side in the cross-section. Note that the mobility enhancement occurs at SOI thickness = 4.5 nm (thicker than 3.2 nm) due to the subband effect [1], which is a one-dimensional confinement of electron’s wave. Let us suppose, although the dimension is different, that two-dimensional subband effect is indispensable in the modeling of this SiNWFET. First of all, we briefly review physical models of RTN amplitude and the density gradient method for modeling the subband effect in the device simulation. Next, we expand the density gradient method to the two dimensional confinement and then perform three-dimensional device simulation of SiNFETs to obtain I-V characteristics and related profiles of potential, carriers, and current densities inside the nanowire. At last, by visually analyzing these profiles together with the simulated I-V characteristics, we can conclude that the RTN amplitude decreases when the carrier density increases in the vicinity of trapped charge along the core of nanowire in the strong inversion region. It is because the wave function is swept out from the boundary inside the nanowire to gather nearby the core of the nanowire. We can also conclude that if a trap locates in the high-K dielectric film above the middle of channel then the RTN amplitude is the maximum in the weak inversion region.

參考文獻


[1] K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata and S. Takagi, "Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm," Digest. International Electron Devices Meeting, San Francisco, CA, USA, 2002, pp. 47-50.
[2] G. E. Moore, "Cramming More Components onto Integrated Circuits", Electronics Magazine, vol. 38, no. 8, pp. 114-117, April 1965.
[3] Jack St Clair. Kilby, "Turning potential into realities: The invention of the integrated circuit (Nobel lecture)." ChemPhysChem 2.8‐9 (2001): 482-489.
[4] Robert N. Noyce, "Microelectronics." Scientific American 237.3 (1977): 62-69.
[5] D. Hisamoto, et. al., "A folded-channel MOSFET for deep-sub-tenth micron era", IEDM Tech. Dig 38 (1998): 1032-1034.

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