可程式化閘陣列之高效率多埠演算法記憶體設計

Efficient Designs of Algorithmic Multi-ported Memory on FPGA

黃琨驊(Kun-Hua Huang)

指導教授 ： 賴伯承

國立交通大學/電機學院/電子工程系所/碩士(2016年)

摘要

無資料

關鍵字

演算法記憶體 ； 可程式化閘陣列 ； 多埠記憶體 ； 高效能 ； 可重組記憶體

並列摘要

無資料

並列關鍵字

Algorithmic memory ； FPGA ； multi-ported memory ； performance ； BRAMs

參考文獻

[3] Lockwood, John W., et al. "NetFPGA--an open platform for gigabit-rate network switching and routing." Microelectronic Systems Education, 2007. MSE'07. IEEE International Conference on. IEEE, 2007.

[4] Lebedev, Ilia, et al. "MARC: A many-core approach to reconfigurable computing." Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on. IEEE, 2010.

[5] Balasubramanian, Raghuraman, et al. "MIAOW-An open source RTL implementation of a GPGPU." Low-Power and High-Speed Chips (COOL CHIPS XVIII), 2015 IEEE Symposium in. IEEE, 2015.

[6] Li, Yan, et al. "Timing analysis of concurrent programs running on shared cache multi-cores." Real-Time Systems Symposium, 2009, RTSS 2009. 30th IEEE. IEEE, 2009.

[17] Yabuuchi, Makoto, et al. "13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists." Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International. IEEE, 2014.