低壓高速動態比較器之實現

Implementation of Low Voltage, High Speed Dynamic Comparators

郭柏均(Bo-Jyun Kuo)

指導教授 ： 蔡嘉明

國立交通大學/電機學院/電子工程系所/碩士(2012年)

https://doi.org/10.6842/NCTU.2012.00103

摘要

本論文設計兩種低壓高速動態比較器，針對核心電路“栓鎖器”做改善，使比較器在低供給電壓操作時時，讓比較器能有足夠得過驅動電壓，保持足夠的轉導，維持高速的運作，並使用65nm CMOS做驗證，使之能夠在0.6伏特時，操作速度然能夠達到GHz的等級。第一個比較器在供給電壓0.6V時，操作速度可達1GHz，偏差電壓(1σ) 為6mV，雜訊大小(1σ)為0.65mV，敏感度僅需3mV即可達到BER=10-9，同時功率消耗僅38μW。第二個比較器在供給電壓0.6V時，操作速度更可高達1.3GHz，偏差電壓(1σ) 為7.5mV，雜訊大小(1σ)為0.5mV，敏感度僅需4.2mV即可達到BER=10-9，同時功率消耗僅64μW。

關鍵字

低壓 ； 高速 ； 動態 ； 比較器

並列摘要

This thesis presents two low voltage, high speed dynamic comparators. It
improves the core circuit “latch architecture”, so the comparators can operate
at low supply voltage. The comparators have the large enough overdrive
voltage to keep the transconductance, so the comparators can maintain the
high speed operation.And realizing comparators in 65nm CMOS. The first
comparator operate at supply voltage is 0.6V, the operating speed is 1GHz,
and the input referred offset(1

並列關鍵字

low voltage ； high speed ； dynamic ； comparator

參考文獻

[1] B. Goll and H. Zimmermann, "A 65nm CMOS Comparator with Modified Latch to Achieve 7GHz/1.3mW at 1.2V and 700MHz/47μW at 0.6V," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2009, pp.328-329,329a

[2] B. Goll and H. Zimmermann, "A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65V," IEEE Transactions on Circuits and Systems II: Express Briefs,, vol. 56, pp. 810-814, 2009.

[3] Jieh-Tsorng Wu, Data-Conversion Integrated Circuits, 2010

[4] David A. Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.

[5] Tsuguo Kobayashi, et al., "A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low–Power Architecture," IEEE Journal Solid-State Circuits,, vol. 28, pp. 523-527, Apr. 1993.