運算放大器電路之整合式階層模擬應用

此篇論文旨將階層式自動合成架構之設計應用於金屬氧化層場效應電晶體運算放大器(CMOS Op-Amp)中。此階層式設計由二階段組合而成-由下而上的探索和由上而下的優化處理。前段步驟主要是經由元件契合(device fitting)的過程求得元件及電路的參數對應關係，再經由效能探索(performance exploration)的過程將元件與電路效能做一個描述性的轉換，藉此找出參考電路的效能極限；後段步驟在於從已搜尋到的電路效能集合中選擇出最適者來導出構成元件的各項參數的最佳模擬解。然而，由於在先進製程裡的參數變異將會造成device fitting的不準確，此由上而下的優化步驟所得之局部區域的最佳結果會經retargeting來做修正。基於Op-Amp參考電路，此篇加強不同電路模型架構的應用，並另其極有效地找出每個範例電路模型的效能。

關鍵字

類比電路最佳化；自動化電路效能探索；類比電路模擬；整合式電路設計；階層運算放大器設計；階層類比電路設計

並列摘要

In this thesis, hierarchical design is employed to the automatic synthesis framework applied to the CMOS Op-Amp circuit. This hierarchical framework is consist of two stage, a bottom-up searching and top-down optimizing. In the bottom-up way, technology device information is transformed into circuit performance domain by device fitting and performance exploration. Then, the appropriate performance among the performance space we have searched is chosen to target the optimal simulation result via our top-down flow. However, the uncertainty of device fitting is damaging on advanced technologies' deviation. This top-down flow will also revise the local optima via retargeting. Based on this Op-Amp circuit, we further enhance this framework on different circuit model, and methods used to find out maximum efficiency of each circuit model will be more efficient.

並列關鍵字

optimization ； performance evaluation ； space exploration ； analogue circuits ； circuit simulation ； integrated circuit design ； differential operational amplifier ； hierarchical global-to-local search process ； integrated hierarchical op-amp circuit synthesis ； integrated hierarchical analog circuit synthesis ； performance mapping ； performance metrics ； opamp circuit design ； trade-off aspect identification

參考文獻

[1] K.-H. Meng, P.-C. Pan, and H.-M. Chen, "Integrated hierarchical synthesis of analog/rf circuits with accurate performance mapping," in International Symposium Quality Electronic Design (ISQED), pp. 1 - 8, March 2011.

[3] P. C. Maulik and L. R. Carley, "Automating analog circuit design using constrained optimization techniques," in IEEE International Conference on Computer-Aided Design (ICCAD), pp. 390 - 393, Nov. 1991.

[4] W. Daems, G. Gielen, and W. Sansen, "Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 517 - 534, May 2003.

[5] M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, "Gpcad: a tool for cmos opamp synthesis," in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 296 - 303, Nov. 1998.

[7] B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw Hill, 1 ed., 2001.

國際替代計量

運算放大器電路之整合式階層模擬應用

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