一個具有寬輸入範圍且基於統計相關性的數位背景校正類比數位轉換器

A Correlation-Based Digital Background Calibrated ADC with Wide Input Range

吳德倫(Teh-Lun Wu)

指導教授 ： 洪崇智 ； 陳巍仁

國立交通大學/電機學院/電機學院電子與光電學程/碩士(2012年)

https://doi.org/10.6842/NCTU.2012.00159

摘要

管線式類比數位轉換器具有高速及中高解析度的特性，因此為可攜式電子產品中經常使用之架構。其可藉由低電壓及功率最佳化設計，降低電路整體功率消耗。然而， 電路的非理想效應會進一步劣化管線式類比數位轉換器的性能，包含飄移電壓、運算放大器的非線性增益及電容的不匹配等效應造成之增益誤差。至今，文獻上有許多校正電路技術發表, 其可藉由離線或背景補償等方式, 提升轉換器電路之性能。
在不同的校正技術中，以統計相關為基底的校正技術(Correlation-based Calibration scheme) 被廣泛的使用著，而分割電容校正技術(split-capacitor Technique)即為實現的一種方式，然而，其架構具有輸入訊號振幅的限制。本論文則是在此架構下提出一個擴展其輸入訊號振幅的方法，並以C 語言描述的行為模型做驗證。模擬結果顯示一具有電容匹配誤差<1%的15位元導管式類比數位轉換器，在輸入訊號振幅等於-0.5dBFS下做校正後其SNDR可由未校正前的10.2bit提升到的14.8bit

關鍵字

類比數位轉換器 ； 校正 ； 背景校正

並列摘要

Pipelined ADCs are widely applied in portable electronic devices due to the features of high speed and medium to high resolution. Its power dissipation can be further reduced by applying low voltage and power scaling techniques. However, the dynamic range of the input signal is severely limited under a low supply voltage. The non-idealities of the data converter, such as offset voltage and gain error caused by OpAmp nonlinearities, and capacitor mismatches, will further degrade its overall performance. Nowadays, several calibration techniques have been proposed in the literature. The performance of the data converter can be enhanced by means of off-line or background calibrations.
Among different calibration techniques, correlation-based calibration scheme is widely adopted. The split-capacitor Technique is one of the power implement method among them. But the architecture has a limited input signal range, This thesis present a modified implement method, based on split-capacitor technique, with wide input range . The architecture is verified by simulation using an an ADC behavior model. The simulation result shows than after calibration, the SNDR of an 15b pipelined ADC with 1% capacitor mismatch can be improved from 63dB to 91dB.

並列關鍵字

analog-ditigal converter ； calibration ； background calibration

參考文獻

[1] K.-Y. Kim, N. Kusayanagi, and A. A. Abidi, “A 10-b 100MS/s CMOS A/D converter,” IEEE Custom Integrated Circuits Conference, pp. 419–422, May 1996.

[2] D. G. Nairn, “A 10-b, 3V, 100MS/s pipelined ADC,” IEEE Custom Integrated Circuits Conference, pp. 257–260, May 2000.

[3] Singh, P.N.; Kumar, A.; Debnath, C.; Malik, R.,“20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process,” IEEE Custom Integrated Circuits Conference, 2007

[5] L. Sumanen, M. Waltari, and K. A. I. Halonen, “A 10-bit 200-MS/s CMOS parallel pipeline A/D converter,” IEEE Journal of Solid-State Circuits, vol. 36, no. 7, pp. 1048–1055, July 2001.

[6] S.-M. Yoo, T.-H. Oh, J.-W. Moon, S.-H. Lee, and U.-K. Moon, “A 2.5V 10b 120MSample/s CMOS pipelined ADC with high SFDR,” IEEE Custom Integrated Circuits Conference, pp. 441–444, May 2002.