碳化矽金氧半場效電晶體特性之研究暨深層暫態能譜分析系統改良

碳化矽擁有寬能隙、高崩潰電場以及高導熱係數，所以是一個適合應用於高溫高壓環境的半導體材料。然而，對碳化矽金氧半場效電晶體而言，較低的通道遷移率是一個很重要的問題。二氧化矽以及碳化矽的介面上有相當多的介面能態，它們會捕捉通道中的載子，進而造成很強的庫倫散射，導致通道遷移率的降低。因此，為了提升通道遷移率以及降低導通阻抗，降低介面能態密度是必需的。在本次研究中，我們選擇稀釋的一氧化二氮氧化去降低介面能態密度。在做碳化矽金氧半場效電晶體的製程之前，有兩個製程上的問題要被先解決，分別是表面粗糙度以及氧化速率。此外，為了能更了解介面能態在能隙中的分佈，我們建立了單脈衝深層暫態能譜系統。深層暫態能譜分析能夠測量出缺陷能階、捕獲截面積，以及缺陷密度。深層暫態能譜分析對於缺陷擁有高靈敏度，而且與其它偵測系統比起來相對容易去架設。它的組成包含暫態電容分析儀以及溫度控制器。有別於之前架設的系統，這次我們採用取樣速度更快的Boonton model 7200脈衝電容儀。由於較快速的取樣時間，訊號強度會隨之增強。我們也使用深層暫態能譜分析系統去量測碳化矽電容之介面能態。而電容量測到的深層暫態能譜訊號是包含介電層缺陷以及介面能態。不容易將這兩種缺陷分離，所以介電層缺陷也會貢獻於用深層暫態能譜分析去萃取的介面能態密度上。因此，用深層暫態能譜分析去萃取的介面能態密度會比用高低頻電容電壓方法來的多。此外，選擇不同的取樣時間能獲得不同的介面能態密度在能隙中的分佈。在之前的研究中，碳化矽的表面在經過高溫退火之後，形成很粗糙的表面。為了解決這個問題，我們準備了兩種來源不同的晶片，一個是來自Cree，另一個則是來自Showa Denko。並且使用了FH-6400以及AZ-6112兩種不同型號的光阻形成碳膜，以研究不同的光阻是否會對表面粗糙度造成影響。結果顯示，不管是用哪種型號的光阻，來自Showa Denko的晶片在經過高溫退火後，皆有相當平整的表面。在之前的研究中，經過1050 oC的閘極氧化後，汲極以及源極區域的氧化層厚度皆遠大於通道區域的氧化層厚度。因此，我們試著降低離子佈植的劑量以降低離子佈植對晶格的破壞。結果顯示，隨著劑量的降低，氧化速率也越來越慢。然而，汲極以及源極區域的氧化層厚度仍然大於通道區域的氧化層厚度。在植入高劑量的區域中，濕氧氧化的氧化速率大於乾氧氧化的氧化速率，這是因為經過高劑量離子佈植的碳化矽晶格，無法在高溫退火後完全修復。此外，若是利用高溫離子佈植的方法就能有效的壓低氧化速率。在本次研究中，我們使用被氮氣稀釋的一氧化二氮氣體去修補介面能態密度。使用了兩種不同的總氣體流量以及三種不同的氧化時間，但是一氧化二氮的濃度保持不變。氧化時間越久，氧化層厚度越厚而且有較好的介面能態密度。當氧化時間長達兩個小時時，介面能態密度的改善將達到飽和，而且不同的一氧化二氮氣體流量並不影響介面能態密度的改善。我們使用高溫離子佈植以及來自Showa Denko的晶片製做碳化矽金氧半場效電晶體。使用三種不同的閘極氧化方法，分別是濕氧氧化、乾氧氧化以及稀釋的一氧化二氮氧化。比較這三種試片的剖面結構發現，稀釋的一氧化二氮氧化的試片比其他兩個條件擁有相對較均勻的氧化層厚度。然而，對濕氧氧化的試片而言，汲極以及源極區域的氧化層厚度仍然大於通道區域的氧化層厚度。由於這異常結構，濕氧氧化試片的汲極電流-閘極電壓特性最差。根據稀釋一氧化二氮的鈍化效應以及剖面結構，此試片不意外地擁有最好汲極電流-閘極電壓特性。在高溫的環境下量測，所有碳化矽金氧半場效電晶體皆有比在室溫下量測較高的導通電流、較高的關斷電流、較好的次臨界擺幅以及較低的臨界電壓。本質載子濃度隨著溫度升高而上升，因此，在高溫環境下會有較高的關斷電流。當溫度升高時，費米能量會往本質能量移動，被捕捉的載子將部分被釋放，導致通道中的載子濃度上升，因此導通電流上升。較低的臨界電壓是因為次臨界擺幅隨著溫度上升變好導致。然而，次臨界擺幅隨著溫度上升變好，這個原因仍然不清楚。此外，在本次研究中，轉移電導已有明顯增進。

關鍵字

碳化矽金氧半場效電晶體；深層暫態能譜分析

並列摘要

Silicon carbide (SiC) is a semiconductor material which is suitable for high power and high temperature application due to its wide bandgap, high breakdown electric field, and good thermal conductivity. However, low channel carrier mobility is an important issue for SiC MOSFET. A large number of interface states in the SiC/SiO2 interface which can capture carriers from channel cause strong Coulomb scattering to channel carriers and thus leads to the reduction of channel mobility. Therefore, interface state density (Dit) must be reduced in order to enhance the channel carrier mobility and thus lower the on-resistance. We choose diluted nitrous oxide (N2O) oxidation to reduce Dit in this work. There are two MOSFET fabrication issues in our last work, surface roughness and oxidation rate, and they must be solved before fabricating good MOSFETs. Besides, we setup a conventional single pulse deep level transient spectroscopy (DLTS) system in order to get more information on the distribution of Dit in the bandgap. DLTS is capable of acquiring the information of the energy distribution, capture cross section, and density of defects. DLTS system has high sensitivity and is relatively easier to be setup compared to the other defect detection systems. DLTS system is composed of a transient capacitance meter and a temperature controller. In this work, we use a capacitance meter of model Boonton 7200 which has a more rapid sampling time than the Agilent B1500A used in our previous work. Due to the faster sampling time, the signal intensity is improved. The Dit of the SiC MOS capacitor is measured by our DLTS system. The DLTS signal of MOS capacitor is composed of oxide trap and interface state. It is hard to separate them apart, so the oxide trap also contributes to the extracted Dit by the DLTS method. Therefore, the value of the extracted Dit by DLTS method is higher than that extracted by the high-low C-V method. Besides, different distribution of the Dit in the bandgap would be achieved by choosing different sampling time. For surface roughness issue, there are many step bunches produced after high temperature annealing in our previous works. We have wafers from two different vendors. One of the wafers is from Cree and the other is from Showa Denko. Two kinds of photoresist are used to study the surface roughness issue. They are FH-6400 and AZ-6112. The carbon layer is formed by baking photoresist at 900 C. Samples from Showa Denko’s wafer show that no step bunches are produced after high temperature annealing no matter what kind of photoresist is used. For oxidation rate issue, the oxide thickness at S/D regions is much thicker than that at channel region after gate oxidation at 1050 oC. We try to reduce the dosages of ion implantation at S/D regions to reduce lattice damage. It is found that the lower the dosage is, the slower the oxidation rate is achieved. However, the oxide thickness at S/D regions is still thicker than that at channel region. The oxidation rate of wet oxidation is higher than that of dry oxidation at the high dosage region because the lattice of SiC under high dosage ion implantation cannot be fully recovered by high temperature post-implantation annealing. Furthermore, using heated ion implantation is a useful way to suppress oxidation rate. N2O gas which is diluted by N2 gas is used to passivate Dit in this work. There are two different total flow rates and three different oxidation time but the concentration of N2O gas is fixed. The longer the oxidation time is, the thicker the oxide thickness is expected and the better the Dit characteristic is achieved. The improvement of the Dit characteristic saturates when the oxidation time is longer than two hours. The flow rate of N2O gas would not affect the Dit characteristic. We use Showa Denko’s wafer and heated ion implantation to fabricate SiC MOSFET. There are three different gate oxidation recipes. They are wet oxidation, dry oxidation, and diluted N2O oxidation. Comparing the cross-sectional transmission electron microscopy (TEM) micrography of all samples, the oxide thickness of the diluted N2O oxidation is relatively uniform than the others. However, for wet oxidation sample, the oxide thickness at S/D regions is still much thicker than that at channel region. Due to this abnormal structure, the ID-VG characteristic of wet oxidation sample is the worst. Due to the passivation effect of the diluted N2O oxidation and the uniform gate oxide thickness, the diluted N2O oxidation sample, not surprisingly, has the best ID-VG characteristic among all samples. For high temperature measurement, all SiC MOSFETs exhibit higher on current, higher off current, better subthreshold swing, and lower threshold voltage than the characteristics at room temperature. The intrinsic carrier concentration is higher at higher temperature, thus the off current is also higher. Because the bulk Fermi energy moves toward to the mid-gap, the trapped carriers would emit and thus the carrier concentration is higher at higher temperature. The lower threshold voltage is attributed to the better subthreshlod swing. However, the mechanism of better subthreshlod swing at higher temperature is still not clear. Furthermore, the transconductance has been significantly improved in this work.

並列關鍵字

SiC MOSFET ； DLTS

參考文獻

[1]. R. N. Hall, “Electron-Hole Recombination in Germanium,” Physical Review, vol. 87, p. 387, July 1952.

[3]. E. Duane Wolley, “Gate Turn-Off in p-n-p-n Devices,” IEEE Transactions on Electron Devices, vol.ed-13, no.7, pp. 590-597, July 1966.

[4]. M. Ostling, “Silicon Carbide Based Power Devices,” IEDM, 2010, pp. 316-319.

[8].Tsunenobu Kimoto, “SiC Technologies for Future Energy Electronics,” Symposium on VLSI Technology Digest of Technical Papers, Honolulu, 2010, pp.9-14.

[10]. B. Ray and R. L. Spyker, “High Temperature Design and Testing of a DC-DC Power Converter with Si and SiC Devices,” IEEE IAS, Seattle, 2004, pp. 1261-1266.

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碳化矽金氧半場效電晶體特性之研究暨深層暫態能譜分析系統改良

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