適用於高速嵌入式記憶體之高速及低功率消耗數位式降壓電路

An Ultra-fast Response and Low Power Consumption Digital Low Dropout Regulator for High Speed embedded Memory Applications

陳瑞隆(Jui-Lung Chen)

指導教授 ： 陳科宏 ； 劉志尉

國立交通大學/電機學院/電機學院電機與控制學程/碩士(2014年)

https://doi.org/10.6842/NCTU.2014.01160

摘要

無資料

關鍵字

數位式降壓電路 ； 嵌入式記憶體 ； 低功率

並列摘要

無資料

並列關鍵字

Digital LDO ； embedded memory ； low power

參考文獻

[6] B. Razavi, Design of Analog CMOS Integrated Circuits. New York, NY, USA: McGraw-Hill, 2001.

[7] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications, and Design, 3rd ed. Hoboken, NJ, USA: Willy, 2003.

[10] R. Ridley, “Current mode or voltage mode?” Switching Power Mag., Oct. 2000.

[11] A. Makharia and G. A. Rincon-Mora, “Integrating power inductors onto the IC-SOC implementation of inductor multipliers for dc-dc converters,” in Proc. IECON’03. 29th Annu. Conf. IEEE, Nov. 2003, vol. 1, pp. 556–561.

[12] G. A. Rincon-Mora, “Active capacitor multiplier in miller-compensated circuits,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 26–32, Jan. 2000.