低溫銅接合製程研究及異質整合平台開發

Development of Low Temperature Cu Bonding and Heterogeneous Integration Platform

黃彥斌(Yan-Pin Huang)

指導教授 ： 陳冠能

國立交通大學/電機學院/電子工程系所/博士(2017年)

摘要

本博士論文研究三維積體電路關鍵技術及異質整合平台開發，內容將著重於接合技術之物理機制及其應用。其中包含兩大部分:超低溫金屬接合技術、及使用高分子接合達其異質整合平台研發。所開發的低溫接合技術可改善三維積體電路在接合技術上所面臨的需多困難，包含熱預算及間距微縮等；另一方面，開發的異質整合平台可克服未來各種微機電系統以及不同基板間之異質整合上的技術困難。
在低溫金屬接合研發中，本研究以暫態液相接合為出發；選用低熔點金屬-銦、錫作為接合材料，接合溫度介於160 °C ~220 °C。並且使用剪力測試，探討熱壓接合參數(溫度、壓力、時間)跟強度之間的關係。在一系列的實驗結果中發現，熱壓接合的情況下接合溫度跟接合時間都不是主要影響強度的因素，推測影響因素為表面金屬氧化層。由於超音波震盪可以去除表面氧化層，因此採用超音波輔助接合測試本實驗架構，最後驗證接合強度的確大幅度提升。
相較於銅柱凸塊暫態液相接合，固相薄膜接合可以有較少的製程步驟並且可以達到更高的密度、更小的間距。本研究中使用表面薄膜鈍化層保護銅防止氧化，以便實行低溫接合。首先在鈍化層的選擇中，考慮自我擴散以及互相擴散所需之能量消耗，探討不同鈍化層跟銅之間的互相擴散行為。其中包含了(1)表面自我擴散 (2)內部體積自我擴散 (3)空缺生成 (4)藉由空隙之互相擴散 (5)藉由空缺所進行之取代型互相擴散。
本論文最後選用Ti以及Pd作為鈍化層進行後續的銅對銅接合測試以及電性分析。以Ti及Pd為鈍化層的銅結構分別可以達到180°C以及150°C的低溫接合。並且經由Kelvin結構實行電性量測以及可靠度測試，其結果顯示電阻值皆沒有明顯變化，證明此結構不受環境影響劣化具有良好的穩定性。
在本研究的第二部份:晶片級異質整合平台。為了能在”晶片”尺寸下完成三維積體電路的堆疊及矽直通穿孔晶片級後製程，本研究提出經由乾膜微影技術製作之承載晶圓，能將多個虛擬晶片(dummy chip)回歸於晶圓等級進而可行微影、矽穿孔、金屬佈線等晶圓級製程驗證，而順利完成垂直聯結之異質整合晶片。

關鍵字

低溫接合 ； 三維積體電路 ； 異質整合

並列摘要

This dissertation focuses on researches of three-dimensional integrated circuit, including development of key technologies and using technologies for the construction of heterogeneous integration platform. Studies focus on the physical mechanism of bonding technology and its applications, including two parts: (1) ultra-low temperature metal bonding technology, and (2) development of the heterogeneous integration platform through polymer bonding. The newly developed bonding technology can solve several current bottlenecks, such as thermal budget and spacing miniaturization. On the other hand, the proposed heterogeneous integration platform can be applied to various micro-electromechanical systems and different substrates.
In low temperature metal bonding, this study used the transient liquid phase connection as the starting material. The metal with low melting point - indium and tin were used as the bonding medium. Bonding temperature was set between 160 °C and 220 ° C. In thermal compression bonding method, the relationship between the bonding parameters (temperature, pressure, and time) and the bonding strength was further discussed through shear tests. After a series of experimental results, in the case of thermal compression bonding, it was found that bonding temperature and bonding time are not the dominant factors. The dominant factor may be the existence of surface oxide layer. Since ultrasonic vibration could remove surface oxide layer, the experimental structure was tested through ultrasonic-assisted bonding. As the results, the bonding strength was improved significantly.
Further, in comparison to transient liquid phase, solid-state film bonding can have fewer process steps, higher density, and smaller pitch. In this study, a surface passivation layer was used to protect copper from oxidation. A low temperature bond was achieved because of the passivation layer. At first, in the selection of passivation layer, diffusion behavior between different passivation layers and Cu was investigated by means of energy consumption in both self-diffusion and inter-diffusion: (1) surface self-diffusion, (2) interior bulk self-diffusion, (3) vacancy formation energy, (4) inter-diffusion through interstitial, and (5) inter-diffusion through substitution.
Finally, Ti and Pd were used as the passivation layer for following Cu-to-Cu bonding test and electrical analysis. Cu layers with Ti and Pd passivation were successfully bonded at 180 °C and 150 °C, respectively. Kelvin structure was used to carry out electrical measurement and reliability test. Electrical results showed good consistency in the resistance values, which proved that the structure has good endurance against environmental degradation.
In the second part of this dissertation “chip-level heterogeneous integration platform”, chip-level post process was demonstrated to achieve heterogeneous integration platform of diced chips. This study proposes a carrier wafer made by dry film lithography, which allows multiple dummy chips to implement lithography, silicon perforation, metal wiring and other wafer-level process validation. Finally, the vertical connection of the heterogeneous integrated chip can be achieved.

並列關鍵字

low temperture bonding ； three dimensional integrated circuit ； heterogeneous integration

參考文獻

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