改良式游標尺環形振盪器時脈抖動量測電路

An Improved Vernier Ring Oscillator for Clock Jitter Measurement

陳曉晴(Hsiao-ching Chen)

指導教授 ： 鄭國興

國立中央大學/資訊電機學院/電機工程學系/碩士(2008年)

摘要

隨著半導體製程的進步，超大型積體電路(Very-Large-Scale-Integrated, VLSI)已經朝向高速、系統晶片整合(System-On-Chip, SOC)的方向發展，各電路間的時脈關係更顯的重要。在系統晶片中，時脈同步電路的時脈抖動量是整個電路效能的重要指標之ㄧ，因此能否正確量測時脈的抖動是非常重要的議題[1]。而鎖相迴路(Phase-Locked Loop, PLL)或延遲鎖定迴路(Delay-Locked Loop, DLL)通常會被用來當作系統的時脈同步元件，但由於系統的時脈同步元件之操作頻率上升，也因此需要更精密的量測儀器，進而提高了測試成本。且經由外部儀器進行量測，則外部雜訊亦容易干擾量測結果，因此內建自我測試電路(Build-In Self Test, BIST)漸形發展。使用BIST電路量測時脈抖動可以減少測試成本、雜訊的影響，且提升量測的速度。
本論文使用的內建時脈抖動自我測試電路，主要架構分為：正緣準位偵測器、環形振盪器、相位偵測器、計數器。利用游標尺的相對量測方式，使用兩組環形振盪器來量測時脈抖動量，因此可以達到固定且較高的解析度，並可以減少晶片面積。在振盪器的延遲元件中，利用金氧半場效電晶體形式的電容(MOS Capacitor)作為延遲控制，當製程變異時，可經由改變振盪週期來達到微調解析度的目的，因此，不管製程變異的情況如何，皆能得到相近值的解析度。
此電路設計經由HSPICE模擬分析，並以CMOS 0.18um 1P6M製程來實現，電路的工作電壓為1.8V，可應用於1.25GHz的時脈訊號之抖動量測，其抖動量測之解析度為5ps，消耗功率為3.1mW。含I/O pad的晶片總面積為1090um × 686um，核心電路部份面積為171um × 71um。

關鍵字

抖動量測 ； 製程變異補償 ； 游標尺

並列摘要

As the improvement of semiconductor technology, the Very-Large-Scale Integrated (VLSI) circuit has moved towards the development of high-speed and System-On-Chip (SOC) applications. Hence, improving timing relationship and synchronization problem among circuits is more important. In a SOC system, jitter is the most important effect in a clock synchronization circuit. Therefore, it is very important topic that how to correctly measure the clock jitter[1]. Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL) is usually used as the synchronous component. With the increased operating frequency, it has higher cost on jitter measurement by external equipment. To utilize the external equipment to measure the clock jitter, the probes of external equipments will induce noise and the measurement result will be different. In view the problem, the Build-In Self Test (BIST) design was developed gradually. Using the BIST measurement circuits to measure the clock jitter can reduce testing cost, decrease the effect of external noise, and speed up the jitter measurement.
In this thesis, the BIST jitter measurement circuit is composed of Edge Detector, Ring Oscillator, Phase Detector, and Counter. Employing the idea of vernier by using two sets of ring-oscillator to measure the timing jitter, as a result, fixed and higher resolution can be reached and chip area is also reduced. By using the MOS capacitor into the delay element of the oscillator, we can change the switch of the MOS capacitor to get a fixed resolution that we want, no matter how process variation changes.
This circuit was simulated by HSPICE and implemented in a CMOS 0.18um 1P6M process with 1.8V supply voltage. The power consumption is 3.1mW and the jitter measurement resolution is 5ps at 1.25GHz input clock application. The chip area is 1090um × 686um and core area is 171um × 71um.

並列關鍵字

jitter measurement ； process variation compensation ； vernier

參考文獻

[1] M. M. Gourary, et al., “A new approach for computation of timing jitter in phase locked loops,” Proc. of Design, Automation and Test in Europe and Exhibition 2000, pp. 345-349, Mar. 2000.

[2] T. Okayasu, M. Suda, and K. Yamamoto, “CMOS Circuit Technology for Precise GHz Timing Generator,” Proc. of Int. Test Conf., pp. 894-902, Oct. 2002.

[4] K. A. Taylor, B. Nelson, A. Chong, H. Lin, E. Chan and M. Soma, “Special Issue on BIT CMOS Built-In Test Architecture for High-Speed Jitter Measurement,” IEEE Trans. on Instrumentation and Measurement, vol. 54, no. 3, pp. 975-987, Jun. 2005.

[6] A. H. Chan and G. W. Roberts, “A Jitter Characterization System Using a Component-Invariant Vernier Delay Line,” IEEE Trans. on VLSI Systems, vol. 12, pp. 79-95, Jan. 2004.

[9] T. Xia and J.C. Lo, “Time-to-Voltage Converter for On-Chip Jitter Measurement,” IEEE Trans. on Instrumentation and Measurement, vol. 52, pp. 1738-1748, Dec. 2003.