Speeding up analog and mixed signal simulation is important in SoC design verification. Modeling circuit blocks by hardware description language for specific circuits and building their behavioral models is an efficient verification approach for AMS systems. In this thesis, we focus on the automatic generation of a behavioral model for arbitrary circuit netlist. By separating the circuit into several building blocks, the complexity of circuit behavior is reduced such that its behavioral model can be built by regression-based approach. With those behavioral models, the verification complexity and the simulation time can be reduced significantly. As shown in the experimental results on several circuits, the proposed approach is able to generate the corresponding behavioral models automatically with good accuracy.