高效率功率放大器與振盪器研製

Design of High Efficiency Power Amplifiers and Oscillators

李哲誠(Che-Chen Lee)

指導教授 ： 張鴻埜

國立中央大學/資訊電機學院/電機工程學系/碩士(2013年)

摘要

本論文主要討論為應用於射頻微波及毫米波高功率高效率之原件設計，使用橫向擴散金氧半場效應電晶體(LDMOS)元件及互補式金屬氧化半導體(CMOS)製程實現。首先，以傳統E類功率放大器為基礎，搭配阻抗補償法，利用Freescale公司所製造的LDMOS電晶體，設計出多種高功率E類寬頻放大器和注入鎖定式振盪器，並且達成寬頻、高效率及高功率輸出目標。
第三章提出一個應用於Q頻段的高效率疊接壓控振盪器(VCO)，使用台積電90 nm LP CMOS製程。為了使壓控振盪器有高功率以及高效率的輸出，因此使用疊接架構及π型迴授網路的設計，量測輸出功率和效率分別達到10.4 dBm和16.1%，振盪頻率可從43.8至49.1 GHz。並且使用了Q值增強架構來改善相位雜訊的表現，使相位雜訊在1 MHz頻率偏移時為-104.63 dBc/Hz。
第四章為一個應用於V頻段的鎖相迴路，使用台積電 90 nm LP CMOS製程實現，並根據第三章設計一個差動疊接壓控振盪器。為了確保疊接壓控振盪器為差動輸出，因此可將壓控振盪器拆成等效奇模態電路和偶模態電路，其奇模態電路必須產生振盪，而偶模態電路則不會。接著藉由鎖相迴路及低抖動的參考頻率，可降低差動疊接壓控振盪器的抖動(jitter)以及相位雜訊。量測相位雜訊在1 MHz頻率偏移時為-86.5 dBc/Hz，其方均根(rms)抖動為307 fs。鎖定頻率可能59.6至60 GHz，輸出功率和效率分別達到7.6 dBm和2.2%。
最後，在第五章總結此篇論文的研究成果。

關鍵字

效率 ； 功率 ； 放大器 ； 振盪器

並列摘要

This thesis discusses design of high power and high efficiency power devices for radio frequency, microwave and millimeter-wave (MMW) applications. The circuits are designed using laterally diffused metal oxide semiconductor (LDMOS) transistors and complementary metal oxide semiconductor (CMOS) process. First, based on the conventional class-E topology with reactance compensation technique, a few broadband power amplifiers and injection-locked oscillators are presented, using Freescale LDMOS transistors. The proposed circuits feature broadband, high efficiency and high power.
A Q-band high efficiency cascode voltage controlled oscillator (VCO) using TSMC 90 nm LP CMOS process is presented in Chapter 3. To achieve both high power and high efficiency output, the cascode topology with π-feedback network is employed in the design. The proposed VCO exhibits a maximum output power of 10.4 dBm, and a maximum efficiency of 16.1%. The tuning frequency is from 43.8 to 49.1 GHz. Also the Q-enhancement circuit is introduced to improve the phase noise performance. The phase noise is -104.63 dBc/Hz at 1-MHz offset.
A V-band phase locked-loop (PLL) using TSMC LP 90 nm CMOS process is presented in Chapter 4. Based on the cascode VCO topology, an innovative differential cascode VCO is proposed for the V-band PLL. To ensure the differential operation for the cascode VCO, the even- and odd-mode analysis is adopted in the circuit design. Moreover, the output phase noise and jitter of the differential VCO can be significantly reduced using the PLL with the low phase noise reference. The measured output power is higher than 7 dBm, over the bandwidth with a dc-to-RF efficiency of 2.2%. The phase noise is -86.5 dBc/Hz at 1 MHz offset with a rms jitter of 307 fs.
Finally, the conclusion is summarized in Chapter 5.

參考文獻

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