三維積體電路中同步降低熱點溫度與電源雜訊之研究

隨著製程的演進，現今超大型積體電路的設計流程變得愈來愈複雜。正因製程技術上的精進，使得晶片的尺寸得以做得更小，但也同時讓整體的花費變得更高。三維積體電路設計主要強調的精神，是將晶片由傳統的二維平面擺放，延伸到可做垂直方向的放置，如此一來，在單位面積上的晶片密度可以得到提升，便可以用較低的花費或較成熟的技術製造相同功能的設計。此外，還可以將不同製程的電路設計，利用晶片堆疊的方式加入到三維積體電路架構當中，即是所謂異質整合的應用。在三維積體電路設計架構中，熱的問題以及電源雜訊的問題將會影響到整體電路運作的效能。本論文提出一個同時處理兩個問題的方法，即加入改善熱點溫度的散熱型矽晶穿孔，以及加入改善電源雜訊的去耦合電容。由於散熱型矽晶穿孔在常溫下即有等效於去耦合電容的能力，且此能力會隨溫度上升而更加增強，因此散熱型矽晶穿孔不僅有散熱的功能且可以利用其電容性質改善電源雜訊。我們將散熱型矽晶穿孔的兩種功能模型化至我們提出的解決方法中，並且在不改變整體平面規劃的面積之下，利用線性規劃的方式，依照需求有效地達成降溫以及改善電源雜訊的問題。若是在現有的條件之下，無法達成設定的目標溫度或是改善的電源雜訊值，則會回報距離目標溫度或是尚需改善電源雜訊的差值。

關鍵字

電源雜訊；熱點溫度；三維積體電路

並列摘要

As the process technology progresses, the design flow of VLSI circuits becomes more and more complicated. Although the enhancing technique makes the chip size reduce, the fabrication cost arises simultaneously. The difference between two dimensional（2D）and three dimensional integrated circuits（3D ICs）is that 3D ICs emphasize the vertical connection between layer and layer, which can certainly arise the chip density, implying that we can obtain the same design with lower cost. Besides, the die-stacking technology of 3D IC provides designs with different technologies on a chip and supports the application of heterogeneous integration. In 3D IC architecture, the thermal and power noise problems affect the performance of the whole chip. In this thesis, we present a method to solve these two problems by simultaneously adding thermal TSVs（TTSVs）for thermal issue and decoupling capacitors（decaps）for power noise issue. Since the unit-area capacitance of a TTSV at the room temperature is equivalent to that of a decap, and the unit-area capacitance of a TTSV is arisen with increasing temperature, TTSVs have the abilities of dissipating thermal and reducing power noise. We model these two abilities into the proposed method. Without enlarging the area of floorplanning, the proposed method can maximize the reduction of the temperature and IR-drop using linear programming under the given target temperature and voltage. If the target temperature or voltage could not be achieved, the differences between the real temperature (voltage) and target temperature (voltage) will be reported.

並列關鍵字

hotspot temperature ； supply noise ； thermal TSVs ； decoupling capacitors

參考文獻

[1] R. Weerasekera, D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, “Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 8, pages 1237-1250, Aug. 2009.

[3] N. Miyakawa, “A 3D Prototyping Chip Based on a Wafer-Level Stacking Technology,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pages 416-420, 2009.

[4] J.-Q. Lu, “3D Hyperintegration and Packing Technologies for Micro-Nano Systems,” in Proceeding of the IEEE, vol. 97, no. 1, pages 18-30, 2009.

[6] T.-Y. Chiang, K. Banerjee, and K. C. Saraswat. ”Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects,” in IEEE International Conference on Computer-Aided Design, pages 165-172, 2001.

[7] S. Lee, T. Lemczyk, and M. Yovanovich. “Analysis of Thermal Vias in High Density Interconnect Technology,” in Proceedings 8th IEEE Semi-Therm Symposium, pages 55-61, Feb. 1992.

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三維積體電路中同步降低熱點溫度與電源雜訊之研究

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