適用高能效微處理器之按需時序臆測設計分析

Analysis of On-Demand Timing Speculation for Energy-Efficient Microprocessors

許庭瑜(Ting-Yu Shyu)

指導教授 ： 林泰吉

國立中正大學/工學院/資訊工程學系/碩士(2013年)

摘要

先進製程在製程（process）、電壓（voltage）、溫度（temperature）以及資料（data patterns）上變異的狀況相當嚴重，在一般考慮最差狀況的設計下在效能將受到很大的影響，可變延遲路徑技術可以避免最差狀況的設計，可以針對一般狀況設計，進而提升效能，而Razor是一個使用電路層級時序臆測的可變延遲路徑技術，是一個有前景的技術，與一般的靜態的方法相比，它可以動態地容忍PVT的變異，但額外的時脈延遲、維持時間（hold time）的限制以及臆測機制多餘的開銷是Razor的問題所在，在本論文中，我們分析我們所提出的按需時序臆測（ODTS；on-demand timing speculation）以及Razor在能效上的差異，為了驗證我們的方法，也實作了加上ODTS方法的微處理器至FPGA。

關鍵字

抗變異 ； 時序臆測 ； 可變延遲

並列摘要

PVTD (process, voltage, temperature and data patterns) variations effect strongly in advanced technology. Worst-case designs have pool performance under high variation environment. Variable latency design is to prevent worst-case design and increase the performance by designing for typical case. Razor is a variable latency design using circuit level timing speculation. It is a promising technology because it dynamically tolerant PVT variations compared with conventional static design approaches. But Razor has some problems: extra clock delay, hold time constraint and overheads of timing speculation. In this thesis, we analyze our proposed ODTS (on-demand timing speculation) and Razor by comparing their energy-efficiency. For verifying our method, we also implement a microprocessor using ODTS in FPGA.

並列關鍵字

Variation tolerant ； Timing speculation ； Variable latency

參考文獻

[1] B. H. Calhoun and D. Brooks, “Can subthreshold and near-threshold circuits go mainstream?” IEEE Micro, Jul.-Aug., 2010

[2] A. P. Chandrakasan, et al., “Technologies for ultradynamic voltage scaling,” in Proc. IEEE, vol. 98, pp. 191-214, Feb. 2010

[3] L. Benini, E. Macii, and M. Poncino, "Telescopic units: increasing the average throughput pipelined designs by adaptive latency control," in Proc. DAC, pp.22-27, Jun. 1997

[4] L. Benini, E. Macii, M. Poncino, and G. De Micheli, “Telescopic units: a new paradigm for performance optimization of VLSI designs,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 17, pp.220-232, Mar. 1998

[5] Y. S. Su, D. C. Wang, S. C. Chang, and M. Marek-Sadowska, “An efficient mechanism for performance optimization of variable-latency designs,” in Proc. DAC, pp.976-981, 2007