最近這幾年, 多輸入多輸出(Multiple Input Multiple Output, MIMO) 技術在無 線通訊的發展過程中備受青睞。而在MIMO系統中, 檢測(detection)屬於很重要的 部分之一, 而通常在這些檢測器中, 會結合QR分解運算來實現, 如SIC(Successive Interference Cancellation) 檢測器、K-best 檢測器等。其中檢測器又可以有硬式檢測 解碼和軟性檢測解碼兩種, 而軟性檢測解碼可以在相同的系統條件下達到較好的系 統效能。本論文主要探討的主題, 在天線數為4 × 4 SDM (spatial division multiplexing) MIMO 系統下, 使用軟性偵測解碼, 並利用LORD(Layered ORthogonal lattice Detector) 演算法, 來實現預處理之QR 分解硬體架構設計。其中, 因為使 用軟性檢測器需傳送軟性(soft) 的事後機率(a posteriori probabilities, APP) 給解碼 器, 但如果使用ML 演算法, 其複雜度會很大且不易實現於硬體架構上, 因此選 用複雜度較低且適合實現在硬體架構上的LORD 演算法做為本論文實現QR 分解 的理論。QR分解部分, 選用TACR(Three Angle Complex Rotation) 演算法, 並且 以CORDIC(COordinate Rotation DIgital Computer)演算法來做硬體上面的實現。此 外, 本論文使用CORDIC 模組在triangular systolic arrays (TSAs) 的架構下, 後面 接了register file 架構, 儲存第一組經過TSA 架構出來的R 和Q 矩陣, 另外, 再 模仿設計出類似TSA 的架構接在register file 後面, 繼續平行做完QR 分解的動 作。在register file 的部分, 利用時序設計, 有效縮短處理時間, 以達到更短的latency 。在硬體實現這部分, 是使用Xilinx ISE 12.2進行Verilog code 的程式撰寫 並驗證(Function verification) 確認結果之正確性, 再以Design Compiler 來進行最 後的Pre-simulation ,其中操作頻率為126.58MHz , throughput rate為15.82M 。
The multiple input multiple output (MIMO) technique has been widely used in the development of wireless communications in recent years. Detection of the transmitted symbols is one of the important part in the MIMO baseband receiver. Generally, some MIMO detectors, such as the SIC and K-best detectors, will rely on the QR decomposition (QRD) at their preprocessing stage. The baseband MIMO detectors can also divided into two categories, the hard-output and soft-output detectors, the latter one can achieve the better efficiency. As a result, the main discussion in this thesis, using soft-output detector in SDM MIMO system, and utilize LORD algorithm to realize the design of hardware architecture of QR decomposition. Because the soft a posteriori probabilitiy is computed and sent to the following decoder in soft-output detector, howeever, using ML algorithm may cause formidable computational complexity and not easy to realize to the hardware architecture. Hence, LORD algorithm is chose to use to do the preprocessing stage of the detection in our dissertation. In QR decomposition, TACR (Three Angle Complex Rotation) algorithm is used and implementing hardware architecture with CORDIC algorithm. The hardware design of register file is connect after the TSA architecture with CORDIC modules, and stored the values of R and Q matrix from TSA. Then design the similar architectures connect after register file in order to parallel-process the other QRD. Timing sequence is very important in register file to achieve the shorter latency. The designed hardware architecture is synthesized and verified in the Xilinx ISE 12.2 environment and also synthesized by Design Compiler to do the final pre-simulation and it can work with frequency 126.58 MHz and the throughput rate is 15.82M.