開發奈米製程下之全數位鎖相迴路自動產生器

Develop An All-Digital Phase-locked Loop Compiler In Nanometer CMOS Technologies

陳貞翰(Chen-Han Chen)

指導教授 ： 鍾菁哲

國立中正大學/工學院/資訊工程學系/碩士(2014年)

摘要

鎖相迴路(PLL)被廣泛地使用於系統晶片(SoC)中。相對於傳統的類比PLL，全數位鎖相迴路(ADPLL)採用數位的設計方法，使其能夠很容易地在先進CMOS製程下與其他的數位電路集合成電路系統。當製程技術或需求規格改變時，重新設計一個PLL時是很耗費時間的。所以為了減少重新設計PLL的時間與努力，使用標準單元(Standard Cell)實現的ADPLLs可以具有最佳的攜帶性，更適合用於SoC設計上。
在ADPLL的所有功能單元之中，數位控制振盪器(DCO)是最重要的組成元件。因為DCO通常佔據了晶片中的最大面積，也是最主要的功率消耗來源。此外，DCO也決定了ADPLL的主要性能，如輸出的頻率範圍、輸出抖動。最重要的是，ADPLL目前已經大量的應用於各種不同的設計需求上，例如: 展頻電路(spread-spectrum clock generator)、快速鎖定(fast settling)頻率合成器。所以，自動化設計流程的ADPLL是必須的，藉以加速整個設計流程。
因為傳統PLL通常鎖定時間都很長，因此導致PLL不常關閉，也因此當系統待命時，一直在運作的PLL的功率消耗就變成SoC待機(Standby)功率消耗的主要來源。若是PLL能快速鎖定頻率及相位，也能讓電路更快地待機，讓PLL早點可以被關閉以減少耗能。
因此，在本論文中，我們設計出透過ADPLL compiler產生及佈局架構彈性、線性的DCO，低耗能、快速鎖定之全數位鎖相迴路來避免掉上述的問題，並以90 奈米製程標準元件庫實現，用以驗證我們所提出的ADPLL compiler設計。

關鍵字

快速鎖定全數位鎖相迴路 ； 全數位鎖相迴路產生器 ； 全數位鎖相迴路 ； 數位震盪器

並列摘要

Phase-locked loop (PLLs) are widely used in a system-on-a-chip (SoC). In contrast to analog PLLs, all-digital phase-locked loops (ADPLLs) use digital design approaches which allows it to be easily integrated with other digital circuits into the systems in advanced CMOS process. In order to reduce the design time and design efforts when processes or specifications are changed, ADPLLs which implemented with standard cells have best portability and suitable for the SoC as compared with analog PLLs.
Among the functional blocks of the ADPLL, digitally controlled oscillator (DCO) is the most critical component. Because the DCO usually occupies the most portions of the chip area and consumes relative large power consumption than the other blocks of the ADPLL. Furthermore, DCO dominates the major performance of the ADPLL, such as the output frequency range, and output jitter. According to different design requirements for realizing an ADPLL for various applications, such as a spread-spectrum clock generator (SSCG), a fast settling ADPLL, an automatic design flow for the ADPLL is demanded in order to speed up the overall design process and reduce design turnaround time.
Traditionally, PLL usually takes long lock-in time. Thus for power management of the SoC, PLL can’t be turned off for reducing the standby power consumption. The continuous operating PLLs often dominate the standby power consumption of the system. If the PLL can quickly achieve lock-in and then the PLL can be turned off for reducing energy consumption.
Therefore, an ADPLL which has a fast settling that generated by an ADPLL compiler with liberty timing files is presented in this thesis. The proposed ADPLL has following characteristics: fast lock-in time, low power consumption and a flexible DCO architecture with high linearity. In addition, the test chip is implemented and tapeouted in 90nm CMOS process to verify the proposed ADPLL compiler.

並列關鍵字

digital control oscillator (DCO) ； Fast Lock-in ADPLL ； ADPLL compiler ； All-Digital Phase-Locked Loop (ADPLL)

參考文獻

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[2] Chao-Wen Tzeng, Shi-Yu Huang and Pei-Ying Chao, “Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 621-630, March 2014.

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