40 奈米製程下開發與設計快速鎖定之全數位鎖相迴路

Design of A Fast Lock-In All-Digital Phase-Locked Loop in 40-nm CMOS Technology

羅啟光(Chi-Kuang Lo)

指導教授 ： 鍾菁哲

國立中正大學/工學院/資訊工程學系/碩士(2015年)

摘要

近年來，系統晶片(SoC)被廣泛的應用在生醫電子、展頻電路、植入式醫療裝置以及無線網路等應用，由於在SoC中，需要供應不同頻率的工作時脈到不同I/O介面，因此，鎖相迴路(PLLs)經常使用在SoC上，以產生多組不同的工作時脈。此外，這些應用的需求在於低耗能及低成本。
隨著先進CMOS製程的開發，工作電壓不斷的下降，傳統PLL在設計上遭遇很大的挑戰。基於time to market的考量，為了減少重新設計PLL的時間與努力，ADPLL採用了全數位的設計方式，以及使用標準元件(Standard Cell)實現ADPLL，不僅加速了設計過程，更增加PLL的移植性，相較於傳統PLL，全數位鎖相迴路(ADPLL)更適合用於SoC上。
由於傳統PLL的鎖定時間都很長，導致PLL需要較長的工作時間。當系統待命時，PLL的耗能即成為SoC待機(Standby)時功率消耗的主要來源。因此，若縮短PLL的鎖定時間，即早鎖定頻率及相位，PLL便可隨需求關閉以減少耗能，快速鎖定的ADPLL變成設計的趨勢。
因此，在本文中，我們提出快速鎖定的全數位鎖相迴路，透過校正及補償機制來降低面積成本的消耗，以及提升鎖定中心頻率的精準度，是本論文的主要目的及貢獻。本論文以40奈米製程標準元件庫實現，並驗證我們所提出的電路架構。

關鍵字

快速鎖定全數位鎖相迴路 ； 全數位鎖相迴路

並列摘要

In recent years, biomedical electronic applications, spread-spectrum clock generators, implantable medical devices, and frequency hopping wireless applications are widely used in system-on-a-chip (SoC). In an SoC, it requires different clock sources for different I/O interfaces. Thus, phase-locked loops play an important role in SoC in order to generate different clock sources. Besides, the primary concern of these applications are low energy and low cost.
While the operation voltage is scaling down with the latest CMOS process, analog PLLs encounter great design challenges. According to time to market, in order to minimize the design time and the design efforts, all-digital phase-locked loops (ADPLLs) are adopted in digital design approaches. In addition, ADPLLs implemented with standard cells can not only speed up the design time, but also improve the portability. As compared with analog PLLs, ADPLLs are more suitable for SoC
Analog PLLs are usually not to be stopped due to the long lock-in time. When the system is in sleeping mode, the PLL power consumption dominates the standby power consumption of the system. Therefore, if PLLs can lock the frequency and phase quickly, the lock-in time can be reduced so that PLLs can be turned off in low power modes. As a result, fast lock-in ADPLLs become more and more popular.
Therefore, in this thesis, we proposed a fast lock-in ADPLL with a calibration method in order to decrease the chip area and improve the accuracy in frequency estimation. In addition, the test chip is implemented and verified in TSMC 40-nm CMOS process with standard cells.

並列關鍵字

All-Digital Phase-Locked Loop (ADPLL) ； Fast Lock-in ADPLL

參考文獻

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[3] Yun-Chen Chuang, Sung-Lin Tsai, Cheng-En Liu, and Tsung-Hsien Lin, “An all-digital phase-locked loop with dynamic phase control for fast locking, ” in Digest of Technical Papers, IEEE Solid-State Circuits Conference (A-SSCC), pp. 297-300, Nov. 2012.

[4] Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, and An-Yeu Wu, “A two-cycle lock-in time ADPLL design based on a frequency estimation algorithm,” IEEE Transactions on Circuits and System II: Express Briefs, vol. 57, no. 6, pp.430 - 434, Jun. 2010.

[5] Yi-Wei Chen and Hao-Chiao Hong, “A fast-locking all-digital phase locked loop in 90nm CMOS for gigascale systems,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1134-1137, Jun. 2014.

[6] Keisuke Okuno, Kana Masaki, Shintaro Izumi, Toshihiro Konishi, Hiroshi Kawaguchi and Masahiko Yoshimoto, “A 2.23ps RMS jitter 3us fast settling ADPLL using temperature compensation PLL controller,” in Proceedings of IEEE International Conference on Electronic, Circuits and System (ICECS), pp. 68-71, Dec. 2014.