雙注入鎖定射頻除頻器之設計

本論文主要研究方向為應用於射頻收發機中頻率合成器所需之頻率除頻器；並使用台積電1P6M 0.18μm CMOS及3P6M 0.18μm BiCMOS製程設計。提出二個分別應用在X頻段、Ku頻段除頻器與一個應用在K頻段的除五除頻器。所提出之雙注入除頻器，採用更簡單的架構提升注入效率。由鎖頻公式知，注入訊號的強度越強，除頻器的鎖頻範圍也會跟著變寬。因此，所提出雙注入鎖定式除頻器，在增強注入訊號強度下，增加了除頻器的鎖頻範圍。第二章之除二除三除頻器採雙注入方式，可操作在除二及除三機制下。在除二時，注入訊號強度0 dBm的鎖頻範圍為7.95 GHz至11.78 GHz。在除三時，注入訊號強度0 dBm的鎖頻範圍為13.39 GHz至16.39 GHz。偏壓1.2V下的功率消耗為6.48 mW。第三章之雙注入鎖定式寬頻除三除頻器，使用了雙注入的方法。在注入訊號強度0 dBm鎖頻範圍由11.78 GHz至14.81 GHz。偏壓為1.2V下的功率消耗為6.12 mW。第四章之直接注入鎖定式寬頻除五除頻器，其特色為包含了一個除二電路，以增加鎖頻範圍及輸出。經模擬與量測證實，本論文提出之雙重注入架構確能有效提升鎖頻範圍。未來的進階研究，可朝超低功耗之注入鎖定除頻器繼續研究。高除數除頻器則需在電路佈局時多加留意各種可能影響訊號的情形。

關鍵字

注入鎖定；雙注入；除頻器

並列摘要

The study of this thesis focuses on the design of frequency divider which is used in the phase lock loop of the wireless transceiver. All the proposed circuits were implemented by TSMC 0.18μm 1P6M CMOS and TSMC 0.18μm 3P6M BiCMOS process. In this thesis, two wide locking-range frequency dividers are proposed for X-band and Ku-band applications; and one injection-locked frequency divider by 5 for K-band application. The dual injection-locked frequency dividers proposed in this thesis demonstrate a simple but efficient method to enhance the injection strength. Based on the locking range formula, the strength enhancement of injection signal will make the locking range wider. Therefore, the proposed ILFD demonstrates dual-injection topology achieving high locking range. In chapter II, a dual-mode and wide locking-range dual injection-locked frequency divider by two and by three is demonstrated. This proposed ILFD can function as divider by two and three. The measured locking-range is from 7.95 GHz to 11.78 GHz (38.8%) with an injection power of 0dBm in divider by two and 13.39 GHz to 16.39 GHz (20.1%) with an injection power of 0dBm in divider by three. The power consumption of the core circuit takes 6.48mW from a 1.2V power supply. In chapter III, a wide locking range dual injection-locked frequency divider by three is demonstrated. This proposed ILFD uses dual direct-injection technique. The measured locking range is from 11.78 GHz to 14.81 GHz (22.8%) with an injection power of 0dBm. The power consumption of the core circuit takes 6.12mW from a 1.2V power supply. In chapter IV, a direct injection-locked frequency divider by five with wide locking range is demonstrated. This proposed ILFD uses the direct-injection technique which includes a direct injection-locked frequency divider by two to enhance the locking range and output power. But the proposed high modulus ILFD suffers a problem from the circuit layout. The measured results do not meet with the expectations. It needs more attentions on the circuit layout. The simulation and measurement results provide the proof of the dual-injection topology proposed in this thesis effectively enhancing the locking-range. In the future, it can support the study on the ultra low power consumption injection-locked frequency divider.

並列關鍵字

Dual Injection ； Frequency Divider ； Injection-Locked

參考文獻

[1] Hamid R. Rategh, and Thomas H. Lee, "Superharmonic injection-locked frequency dividers", IEEE J. Solid-State Circuits ,vol.34,no.6,pp.813-821,Jun 1999.

[2] Hui Wu, and Ali Hajimiri, " A 19GHz 0.5mW 0.35µm CMOS Frequency Divider with Shunt-Peaking Locking-Range Enhancement," in IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, 2001, pp.412-413.

[3] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004.

[4] Chung-Chun Chen, Hen-Wai Tsao, and Huei Wang, "Design and Analysis of CMOS Frequency Dividers With Wide Input Locking Ranges," IEEE Trans. Microw. Theory Tech., vol.57, no.12, pp.3060-3069, Dec. 2009.

[5] Sheng-Lyang Jang, Che-Yi Lin, and Chien-Feng Lee, "A 0.35-um CMOS switched-inductor dual-band LC-tank frequency divider," VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on , vol., no., pp.240,242, 23-25, April 2008.

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雙注入鎖定射頻除頻器之設計

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