CMOS-MEMS及IPD晶片天線設計與量測系統

Design of CMOS-MEMS and IPD Chip Antenna and Measurement System

林俊奇(Chun-Chi Lin)

指導教授 ： 張嘉展

國立中正大學/工學院/電機工程學系/博士(2015年)

摘要

本論文針對晶片天線之設計挑戰，利用不同製程之優勢提出一系列零階振盪之架構並針對相關衍生問題進行探討。為了有利於CMOS系統單晶片之整合，首先，以零階振盪為架構基礎的晶片天線分別以0.35/0.18-μm COMS/CMOS-MEMS製程進行設計製作。第一顆晶片天線設計在40 GHz並使用0.35-μm CMOS-MEMS製程。其天線增益為−16.75 dBi，且天線面積為0.74 × 0.32 mm2。第二顆天線將頻率提升至60 GHz亦使用0.35-μm CMOS-MEMS製程，並延伸接地面以提升天線增益。其量測增益為−10.01 dBi，且天線面積為1.00 × 0.41 mm2。第三顆天線則使用0.18-μm CMOS製程，透過接地面移升至最上層金屬並增加兩條槽孔以擴展天線頻寬。其天線增益為−11.71 dBi，而面積為0.975 × 0.375 mm2，操作頻寬可達12 GHz以上。另外我們更進一步整合MEMS致動器與指叉電容，透過指叉電容之位移達到頻率可調之目的，此H形槽孔天線利用0.18-μm CMOS-MEMS製程進行設計。其魚骨結構有效降低致動電壓至38V。其切換頻率分別為 43、47、50.5、54及57.5 GHz，天線增益分別為−16 dBi、−12.8 dBi、−11.3 dBi、−9.2 dBi及−7.9 dBi, 晶片面積為1.2 × 1.2 mm2。
為了克服矽基板的強烈損耗，本論文亦使用IPD製程進行設計，並整合4 × 4巴特勒矩陣與1 × 4雙邊偶極天線陣列，實現一切換波束之相位天線陣列晶片。晶片面積為4.93 × 4.93 mm2。此相位天線陣列成功產生指向60°、15°、−12.5°及−55°之波束，其天線增益範圍為2.5–4.3 dBi。
研究過程亦發現矽基板尺寸會對天線特性產生影響，故殘留效應及改善方法亦在本文中被探討。除藉由NTN層的使用，提高矽基板阻值以降低矽基板損耗。此外亦利用一金屬圍阻牆限制輻射電場之範圍，本論文透過一系列的天線製作進行驗證。
本論文另一貢獻為on-wafer探針量測之遠場晶片天線量測平台之設計與改良。第一代量測平台整合既存之探針平台進行量測。第二代平台進一步使用步進馬達提升量測角度之解析度，創新的Y型晶片載台及可旋轉之探針載台可使此平台應用更具彈性。

關鍵字

天線量測系統 ； 相位天線陣列 ； 晶片天線 ； 零階諧振

並列摘要

This dissertation is focused on the study of on-chip antenna design. In order to facilitate the integration of CMOS single-chip system, several on-chip antennas based on zeroth-order resonance (ZOR) concept have been designed and fabricated using 0.35 / 0.18-μm COMS / CMOS-MEMS technology. The first antenna size is designed at 40 GHz and the measured antenna gain is −16.75 dBi. The gain is enhanced to −10.01 dBi when the frequency is increased to 60 GHz with larger ground plane. A 60-GHz, 0.18-μm CMOS flipped antenna is also investigated by placing the ground on the top. The operation bandwidth is up to 12 GHz. A H-slot antenna driven by a multi-state electric actuator is designed in 0.18-μm CMOS-MEMS technology, aiming to frequency reconfigurability. The frequencies of this antenna can be switched to 43, 47, 50.5, 54 and 57.5 GHz, and the correspondent antenna gain is −16, −12.8, −11.3, −9.2, and −7.9 dBi, respectively.
In order to overcome the intense loss of the silicon substrate, the IPD process is also investigated in this work. A 60-GHz phased antenna array, which consists of a 1 × 4 double-sided dipole antenna array and a four-way Butler matrix, is designed using glass-IPD technology. The overall chip size is 4.93 × 4.93 mm2. The measurements show that the four beams pointing to 60°, 15°, −12.5° and −55° are successfully generated with radiation gains of 2.5–4.3 dBi.
Since the size of the residual silicon substrate can affect the on-chip antenna performance, we provide several novel insights into the problem. We proposed to pave NTN layer underneath the antenna to increase substrate-resistivity and to build the bounding metal wall to confine the substrate current. Those approaches are demonstrated by a series of on-chip antenna design.
Two far-field on-chip antenna measurement platforms based on on-wafer probing are also designed in this work. The first system is constructed upon the existing probe station with manually angular rotation. The 2nd measurement platform adapts a step motor for automatically angular rotation. A novel Y-shaped chip carrier and rotatable probe carrier are proposed to increase the system flexibility.

並列關鍵字

Phased antenna array ； Integrated passive device ； CMOS/COMS-MEMS ； on-chip antenna ； zeroth-order resonance ； On-chip antenna measurement system

參考文獻

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