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  • 學位論文

注入鎖定多推式振盪器分析與設計

Design and Analysis of Injection Locking Multiple-push Oscillator

指導教授 : 吳建華
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摘要


此研究探討振盪器操作頻率超過單一顆電晶體最大振盪頻率(fmax)之作法。將多個電晶體串接形成迴路產生振盪,再將每一級輸出引出,其總和輸出諧波部份互相抵消及部份同相合成。 透過台積電0.18μm CMOS製程。首先設計四推式振盪器,核心偏壓為0.6 V,消耗功率為13.03 mW。振盪基頻頻率在6.45 GHz,四倍頻諧波頻率為25.8 GHz,其大小及抑制分別為-19.59 dBm和19.79 dBc,相位雜訊為-85.07 dBc/Hz。再設計以主動平衡器注入之注入鎖定四推式振盪器,核心偏壓為1.4 V,功率消耗為111 mW。自由振盪基頻頻率在14.17 GHz,四次諧波頻率為56.68 GHz。注入頻率為14.17 GHz、功率強度為14 dBm訊號時,可鎖定輸出一四次諧波功率,其大小為-22.84 dBm,但無諧波抑制。為改善諧波抑制另設計結合威爾金森架構之注入鎖定倍頻器,核心偏壓為0.64 V,功率消耗為21.3 mW。自由振盪基頻頻率在6.2 GHz,四次諧波頻率為24.8 GHz。注入頻率為6.25 GHz及功率強度為-5 dBm訊號時,可鎖定輸出一四次諧波,其大小為-19.54 dBm,諧波抑制效果為13.2 dBc,相位雜訊在偏移頻率1 MHz為-111.77 dBc/Hz。 除此之外,另以分離元件型式探討注入鎖定三推式倍頻器之設計與實現。核心偏壓為2 V,功率消耗為56.2 mW。自由振盪基頻頻率在0.7 GHz,三次諧波頻率為2.1 GHz。注入頻率為0.7 GHz及功率強度為0 dBm訊號時,可鎖定輸出一三次諧波功率,其大小為9.28 dBm,諧波抑制效果為14.7 dBc,相位雜訊在偏移頻率1 MHz為-106.93 dBc/Hz。

並列摘要


A study of the oscillator operated close to the limitation of transistor’s fmax is investigated by multiple transistors cascaded in ring and then oscillation happens due to feedback, while the even mode is suppressed and the odd mode currents cancels out at the output combining node. By this concept, in 0.18μm CMOS process, a 25.8 GHz quadruple-push oscillator was implemented with the output power -19.59 dBm (13.03 mW), in the meanwhile the fundamental and the other unwanted harmonics being suppressed to 19.79 dBc lower. As injection-locking applied in the second design with active balun, it takes 111 mW from 1.4 V supply by 0.18μm CMOS process. The output power is -22.84 dBm with an injection power of 14 dBm at 14.17 GHz, but the unwanted harmonic suppression is still too high. In order to overcome this shortcoming of poor harmonic suppression, a Wilkinson combining structure was used in the third design by 0.18μm CMOS process, it takes 21.3 mW from 0.64 V power supply. The output power is -19.54 dBm with an injection power of -5 dBm at 6.25 GHz while the fundamental and the other unnecessary harmonics were suppressed to 13.2 dBc. Furthermore, a 2.1 GHz injection-locked triple-push oscillator in discrete module was implemented with output power 9.28 dBm (56.2 mW) as injection power being 0 dBm at 0.7 GHz. Both of fundamental and the second harmonic were suppressed to 14.7 dBc.

參考文獻


[2] 楊清淵、張智翔,低電壓0.13微米互補式金氧半導體電壓控制振盪器與倍頻器,興大工程學刊,第二十一卷,第一期,2010。
[1] 高宏瑋,頻率產生電路之注入鎖定機制強化,碩士論文,國立中正大學,2013。
[3] V. Puyal, A. Konczykowska, P. Nouet, S. Bernard, S. Blayac, F. Jorge, M. Riet, and J. Godin, “DC-100-GHz frequency doublers in InP DHBT technology,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 4, pp.1311–1318, Apr. 2005.
[4] klymyshyn, Z. Ma, “Active frequency-multiplier design using CAD”, IEEE Trans. Microw Theory Tech., vol. 51, no. 4, Apr. 2003.
[5] M. C. Chen and C. Y. Wu, “Design and analysis of CMOS subharmonic injection-locked frequency triplers,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 8, pp. 1869–1878, Aug. 2008.

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