具加熱晶片之印刷電路板於隨機振動與熱效應之耦合分析與驗證

印刷電路板於熱效應下受隨機振動之耦合分析為重要議題。利用加熱晶片接合於印刷電路板以探討其熱效應為一新設計，本文透過配置四顆加熱晶片之印刷電路板進行不同熱效應之振動特性分析，並透過有限元素分析及實驗模態分析進行模型驗證。首先透過電源供應器施加直流電壓給加熱晶片，使其產生熱源，探討印刷電路板溫度分佈及驗證，並將其延伸至不同邊界與不同熱效應之印刷電路板振動特性分析及驗證，確立不同熱效應與不同邊界之有限元素模型等效於實際結構，以完成模型驗證。運用印刷電路板於固定邊界驗證成功之有限元素模型，依照JSD22-B103-B振動試驗規範進行頻譜響應分析，量測印刷電路板上之加速度功率頻譜密度函數，由理論及實驗分析所得結果確認分析模型之合理性，再進一步分析印刷電路板於不同熱效應耦合隨機激振下之應力分佈情形，並預測印刷電路板可能發生疲勞破壞之區域。透過本文建立隨機振動耦合熱效應之分析與實驗方法，未來可作為印刷電路板之設計分析參考。

關鍵字

加熱晶片；熱效應；隨機激振；有限元素分析；實驗模態分析；模型驗證

並列摘要

Coupling effects of both thermal and vibration loadings on printed circuit board (PCB) are of interest. This work aims to study the random vibration excitation of PCB with four heating ICs that are used to emulate the temperature elevation during operations. Two levels of heating conditions as well as without heating are considered in this work. The vibration tests according to JESD22-B103-B are carried out to measure the random vibration response of PCB under the conditions of both with and without heating. The finite element (FE) model of PCB with heating ICs is constructed and performed spectrum response analysis with and without thermal effects. The temperature distributions on PCB are first verified and shown good agreement between finite element analysis (FEA) and experiments. The power spectral density (PSD) functions of the acceleration on the PCB in heating are also obtained and compared for both FEA and experiments. The RMS accelerations on the PCB can be calculated and matched well between the analytical and experimental results. The fatigue evaluation due to coupling loadings from thermal and vibration effects on the PCB is also addressed. This work presents the systematic approaches in studying spectrum response analysis of PCB with both thermal and vibration coupling loads and shows a very good agreement results between FEA and experiments.

並列關鍵字

printed circuit board (PCB) ； heating IC ； random vibration ； thermal loading ； spectrum response analysis

參考文獻

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31. 梁秀瑋，2010，隨機振動與熱效應複合負載下之封裝體錫球應力預測分析，碩士論文，國立屏東科技大學，屏東。

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7. Lai, Y. S., Yang, P. F., Yeh, C. L., and Kung, H. Y., 2005, “Board-level Reliability of Chip-scale Packages Subjected to JEDEC Drop Test Condition,＂ Proceeding of the IMAPS-Taiwan 2005 International Technical Symposium Program Conference, Taipei, pp. 1-6.

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具加熱晶片之印刷電路板於隨機振動與熱效應之耦合分析與驗證

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