3D晶片異質整合I/O擺置設計

Chiplet I/O Placement Design for 3D Heterogeneous integration

麥凱宙(Hoi-Chau Mak)

指導教授 ： 黃有榕

共同指導教授 ： 潘宗龍(Chung-Long Pan)

義守大學/智慧科技學院/電子工程學系/碩士(2022年)

摘要

3D晶片異質整合I/O擺置設計，將多個不同性質的電子元件整合進單系統級封裝中（System in Package，SiP），已成為產業技術的主流趨勢。而小晶片(Chiplet）的異質整合被視為延續摩爾定律的重要關鍵技術。由於小晶片的良率較好且能大幅降低研發成本，電子產品設計朝向小晶片架構發展，更能進一步加速高階電子系統的發展。本論文研究Chiplet擺置方法對訊號傳輸效能的影響，和一般矽導通孔(Through Silicon Via; TSV)訊號傳輸不同，Chiplet擺置方法為藉由晶片與晶片間非接觸式電容耦合通訊產生訊號傳輸。此外由於差分信號(differential signal)具有抗干擾能力強，信噪比高，輻射小和頻寬容量大等優點，本論文探討三種不同的晶片擺置方法分別是：Side Differential，Corner Differential，Butterfly Differential，同時考慮不同配置時晶片間不同程度的overlap以及不同操作頻率1GHz-10GHz情況下找岀傳輸效率最好的擺置條件。本研究利用電腦輔助工程分析軟體（ANSYS HFSS）模擬分析不同擺置方法的訊號傳輸結果。最終研究比較發現使用Butterfly Differential的擺置方法能取得最佳的差分信號傳輸效果。

關鍵字

無

並列摘要

The 3D heterogeneous integration design which integrates multiple electronic components of different properties into a single system-in-package (SiP), has become the mainstream trend in industrial technology. The heterogeneous integration of chiplets is regarded as an important key technology to continue Moore's Law. Since the yield of small chips is better and the R&D cost can be greatly reduced, the development of electronic product design toward the structure of small chips can further accelerate the development of high-level electronic systems. This thesis studies the influence of chiplet placement method on signal transmission performance. Different from the general Through Silicon Via (TSV) signal transmission, the chiplet placement method is based on signal transmission through chip-to-chip capacitive coupling communication. In addition, because the differential signal has the advantages of strong anti-interference ability, high signal-to-noise ratio, small radiation and large bandwidth capacity, this thesis discusses three different chip placement methods: Side Differential, Corner Differential, Butterfly Differential configurations. At the same time, consider different degrees of overlap in different configurations and different operating frequencies from 1GHz to 10GHz to find the best placement conditions for transmission efficiency. In this study, the computer-aided engineering analysis software (ANSYS HFSS) was used to simulate and analyze the signal transmission results of different placement configurations. The final research results found that the placement method of Butterfly Differential can achieve the best differential signal transmission effect.

並列關鍵字

none

參考文獻

[1]. Moore’s Law – Now and in the Future https://www.intel.com/content/www/us/en/newsroom/opinion/moore-law-now-and-in-the-future.html

[2]. A. Chow et al., "System Considerations for Wireless Capacitive Chip-to-Chip Signaling，"Radio-Frequency Integration Technology (RFIT)， 2011 IEEE， 2 Dec. 2011.

[3]. Yu-Jung Huang, Mei-Hui Guo, and Cheng-Han Chua “Differential Pad Placement Design of a Capacitive Coupling-Based Stacked Die Package” IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 7, NO. 7, JULY 2017.

[4]. John Park “Chiplets and Heterogeneous Packaging AreChanging System Design and Analysis” Cadence, 2020.

[5]. Yenai Ma, Leila Delshadtehrani, Cansu Demirkiran, Jos´e L. Abell´an, Ajay Joshi “TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems” 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021.