- 學位論文
超高畫質高效能視訊編碼器晶片之演算法及架構設計
Algorithm and Architecture Design of Bandwidth Efficient HEVC Encoder for 8K UHDTV Applications
若您是本文的作者，可授權文章由華藝線上圖書館中協助推廣。
摘要
視訊日益廣泛地運用在各種不同的應用情境中。以網路頻寬而言，預計2014年九成的網際網路頻寬都將用來傳遞視訊信號。為了求得更真實的廣視角體驗，未來視訊解析度的要求也將提升到7680x4320p的超高視覺(SHV)解析度。在此超高解析度下，目前的H.264/AVC視訊壓縮技術將無法提供足夠的壓縮率。次世代的高效能影像壓縮標準(HEVC)將比前一代的H.264/AVC高出52%的壓縮能力，足夠提供4320p的壓縮能力。然而，其對於記憶體頻寬的要求與複雜度均大幅提高，需要有新的硬體架構設計法則。 在本篇論文中，我們提出了一單晶片HEVC視訊編碼器的硬體設計，我們針對記憶體頻寬與複雜度，提出了高複雜度的模式決定演算法，3層記憶體階層架構，以及畫面層級過濾流程。此視訊編碼器最高能提供8192x4320p畫素的即時每秒30張的編碼能力，使用28奈米製程製作，總面積為25mm2 , 8350K等效邏輯閘。比較之前所提出針對H.264設計的系統，在同樣的品質下，我們所提出的系統可節省62%的頻寬。
並列摘要
Video is increasingly used in a wide variety of applications. In the future, more than 90% of internet traffic will be video in 2014. While the bandwidth-consuming video is more and more used, resolution requirement on the other hand is going up to 8K UHDTV/SHV, making bandwidth a serious problem. To support such high resolution video for mass usage, video compression is very important. The next generation standard H.265/HEVC provides more than 50% compression rate compared with H.264/AVC, enabling 4K/8K UHDTV applications. However, the bandwidth and complexity problem of H.265/HEVC at UHDTV poses new challenges to video codec designers. These problem needs to be solved and least amount of quality loss should expose. In this dissertation, we proposed a single-chip bandwidth efficient H.265/HEVC encoder that supports real-time encoding of 8192x4320p at 30fps. Proposed low-cost high complexity mode decision hardware architecture supports complex prediction modes in H.265/HEVC. For loop filtering, we proposes some hardware-oriented hardware architecture that supports non-deblocking loop filtering efficiently. In addition, 3-level memory architecture supports huge bandwidth requirement for motion estimation. At system level, bandwidth-efficient frame-level pipeline is proposed and saves extra bandwidth. The proposed system is also implemented in chip. The core size of the chip is 25mm^2 which contains 8350K gates with 7.55MB on-chip SRAM using 28nm CMOS Technology. The coding gain is over 62% above all the previous work, and bandwidth efficiency is also highest.
參考文獻
[1] P. G. J. Barten, "Evaluation of subjective image quality with the square-root integral method," vol. 7, pp. 2024 – 2031, Oct. 1990.
[4] D. Zhou, G. He, W. Fei, Z. Chen, J. Zhou, and S. Goto, "A 4320p 60fps h.264/avc intra-frame encoder chip with 1.41gbins/s cabac," in VLSI Circuits (VLSIC), 2012 Symposium on, june 2012, pp. 154 –155.
[9] "Video coding for low bit rate communication," in ITU-T Recommendation H.263, May 1996.
[10] "Video coding for low bit rate communication," in ITU-T Recommendation H.263 version 2, September 1997.
[11] "Video coding for low bit rate communication," in ITU-T Recommendation H.263 version 3, February 1998.
延伸閱讀
- Chen, C. W. (2006). 視訊格式轉換晶片之設計及實現 [master's thesis, Tatung University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0081-0607200917232228
- Tsai, C. H. (2012). 可應用於超高畫質電視之 H.264 CABAC 編碼器彈性硬體架構設計與實現 [doctoral dissertation, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2012.00562
- 林易興（2010）。應用於電路交換型晶片網路之高效率通訊排程方法設計與實現〔碩士論文，國立臺北科技大學〕。華藝線上圖書館。https://doi.org/10.6841/NTUT.2010.00310
- Correa, G., Palomino, D., Diniz, C., Bampi, S., & Agostini, L. (2012). Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder. VLSI Design, 2012(), 303-322. https://doi.org/10.1155/2012/748019
- Huang, Y. W. (2004). Algorithm and Architecture Design for Motion Estimation, H.264/AVC Standard, and Intelligent Video Signal Processing [doctoral dissertation, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2004.01450