具可變濾波迴路之可程式頻率合成器設計

DESIGN OF A PLL WITH PROGRAMMABLE FREQUENCY SYNTHESIS AND ADAPTABLE LOOP FILTER

張信隆(Hsin-Lung Chang)

指導教授 ： 黃淑娟

大同大學/電機資訊學院/電機工程學系所/碩士(2005年)

摘要

本論文敘述以TSMC 0.35um 1P4M 技術實現一中心頻率為480MHz具可變濾波之可程式頻率合成器。480MHz 是應用於USB2.0 的規格。 此頻率合成器的頻率範圍為250MHz~500MHz，也可應用在其他數位時脈電路。但是也因為頻率範圍廣,衍生出其他不穩定因素，影響鎖相迴路的效能。文中將討論其發生原因， 同時詳細說明如何應用數位電路作控制， 以產生不同頻率， 達成頻率合成的功能。此外，可變率波迴路也是利用數位控制電路, 切換不同的電阻值， 獲得適合的頻寬， 來改善效能，以減少或解決鎖定時間和迴路穩定性的問題。
我們使用HSPICE和MATLAB來完成電路及行為模擬。最後，我們討論鎖相迴路的實現。為了避免因雜訊及寄生效應而降低電路的效能， 我們列出佈局所應該注意的事項，並完成整個floor plan。整個電路的佈局面積為207.925*305.225(um2)。其post simulation 的結果，當震盪頻率480MHz時,鎖定時間32us，切換震盪頻率為389MHz時，鎖定時間18us，516MHz時為22us，功率消耗14.6494mW.

關鍵字

可程式頻率合成器

並列摘要

This thesis describes a PLL (center frequency: 480MHz applied in USB2.0) with programmable frequency synthesis (frequency range: 245.6MHz~551.12MHz). An adaptable loop filter is employed to tune the damping factor and to stabilize the loop. First, the stability of PLL is discussed. Then, we describe how to implement the frequency synthesis with programmable counter in detail. To solve the problem of the long settling time and unstable, we present the concept of the adaptable loop filter design flow. The digital decoders control the transistors to select the proper resistor value to avoid to the PLL under unstable situation.
Both HSPICE and MATLAB are used to verify the performance of the PLL in circuit and behavioral levels. Finally, we describe the layout issues for the PLL, including noise coupling and parasitic effects. The PLL will be implemented by TSMC 0.35um 1P4M process, and the layout area is 207.925*305.225(um2). The post-simulation result shows that the locking time of the PLL is about 32us, and the power dissipation is 14.6494mW for a 3.3V supply.

並列關鍵字

PROGRAMMABLE FREQUENCY SYNTHESIS

參考文獻

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