以IA-64架構為基礎的指令壓縮研究

A Study of Instruction Compression Based on IA-64 Architecture

楊上毅(Shang-Yi Yang)

指導教授 ： 謝忠健

大同大學/電機資訊學院/資訊工程學系所/碩士(2007年)

摘要

因為現今許多數位訊號處理器是採用超長指令字元的架構來進行處理，所以我們將重點放在超長指令字元的處理器上面，希望之後能對其他的超長指令字元的處理器作一般化的處理。
在資料壓縮方面，較常看到的論文或是較直覺的想法就是利用建立表格的方式來消除重複出現的項目，以減少空間的佔據，但是以超長指令字元的指令來說，一個長指令又包含許多指令，而建表又是對一個長指令來建表，所以裡面有許多重複的項目還是沒有被消除掉，所以我們先對指令的欄位來做分析，希望能把欄位分的更細，細分成數個欄位之後再做統計的工作，統計完後再用簡單的編碼方式來進行資料的壓縮，來達到更有效的對指令進行壓縮。
在這裡我們把目標放在英特爾架構-64(IA-64)處理器上面，因為此架構是屬於市面上已有在販售的產品，所以在實際執行上應該不會有太大問題，而且關於這一架構的資料都很齊全，所以我們實驗模擬也都是以相同架構的模擬器為主，而經由實驗模擬顯示，整體指令壓縮率最高可達到63.1%。

關鍵字

超長指令字元、指令壓縮、英特爾架構-64

並列摘要

Because of many DSPs (Digital Signal Processors) adopt the VLIW (Very Long Instruction Word) architecture to process the signals, we will focus on the VLIW processors; hope to make a normal processing in other VLIW processors in the future.
In data compression, the scheme in many papers or the intuitional idea is constructing a table to eliminate the duplicate items and to decrease the program space in the memory. In the instructions of VLIW Processor, a long instruction include many instructions, but constructing a table is for a long instruction, not an instruction, so there still are many duplicate items not be eliminated. First, we will analyze the fields of instruction to find more attenuate fields, after that, to calculate the fields which is the most frequencies, when finish the work, we use the simple encoding method to compress the data, to get more compression ratio.
We will focus on the Intel Architecture – 64-bit processor, because the architecture is on market now, it does not have problems to execute in real world, and the information about the architecture are complete, so we use the same architecture to run the simulator, and via experimental simulation, the proposed technique has achieved the best compression ratio to 63.1%.

並列關鍵字

VLIW、Instruction compression、IA-64

參考文獻

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