AES 加解密晶片之有效率可程式化邏輯陣列實現

An Efficient FPGA Implementation of Advanced Encryption Standard Chip

王廷富(Ting-Fu Wang)

指導教授 ： 汪順祥

大同大學/電機資訊學院/通訊工程研究所/碩士(2008年)

摘要

在本論文，我們提出有效率可程式化邏輯陣列(FPGA)之AES 加密演算法實 現。所提出的設計是基於管線處理的架構，展開10 次AES 回合，用較簡易的硬 體架構以得到較高的總處理能力及最佳的操作頻率。所實現的AES演算法包含加 密器和解密器，適合大部份內嵌式的應用，例如無線的裝置、智慧卡等等。最後， 我們使用Verilog 語法並配合Xilinx ISE 發展系統與ModelSim 模擬器，驗證實現 AES晶片的設計。

關鍵字

加解密晶片 ； 可程式化邏輯陣列

並列摘要

In this thesis, we propose an efficient Field Programmable Gate Arrays (FPGA)
to implement Advanced Encryption Standard (AES) algorithm. The proposed design
is based on the pipelined architecture that unrolls the 10 AES rounds to ensure the higher throughput, easer hardware architecture and optimized frequency. This implementation includes encryptor and decryptor which fit the most embedded applications, such as wireless devices, smart card and so on.
We use Verilog, Xilinx ISE and ModelSim simulator to implement the chip
design.

並列關鍵字

AES ； FPGA Implementation

參考文獻

Reconfigurable Hardware and its Application to Fast and Compact AES Rijndael,” The Field Programmable Logic Array Conference, Monterey, California , pp.216-224, 2003.

International Conference on Application-Specific Systems, Architectures and

[4] W. McLoone and J.V. McCanny, “Rijndael FPGA implementation utilizing

AES Candidates using Reconfigurable Hardware,” The Third Advanced

[6] A. Dandalis et al., “A Comparative Study of Performance of AES Candidates