採用可調式共振器之雙取樣三位元四階帶通雜訊耦合差和調變器設計

在本篇論文中，我們提出一可調式切換電容(SC)共振器之雙取樣三位元六階帶通差和調變器。它藉由可調式切換電容共振器及量化雜訊耦合技術，僅需三顆放大器即可實現六階差和調變器，使整體達到較低的功率消耗。採用前饋式架構的可調式共振器能降低輸入訊號失真，在多位元量化器中能明顯的減少電路複雜度並且節省晶片面積。且藉由共振頻率的調整可增進在低超取樣頻率(OSR)情況下之訊號對雜訊及失真比(SNDR)。此外，利用雙取樣技術，不但提高取樣頻率且可舒緩放大器速度上的規格要求。並且在量化器之前使用主動式加法，能避免訊號受寄生效應及突波回授雜訊影響。此加法器可同時用來提供量化雜訊耦合以增加差和調變器的有效階數。另外，我們還提出排序動態元素匹配架構來改善電容不匹配所造成數位/類比轉換器不線性的問題。整體設計流程首先利用MATLAB 及SIMULINK來驗證系統穩定度及評估整體效能。接著利用Hspice作電晶體層級的模擬，最後採用TSMC 0.18m CMOS 1P6M實現電路設計，使用1.5伏電壓，調變器的時脈頻率為40MHz (相當於80MHz的取樣頻率)，輸入中心頻率為20MHz。在頻寬為2.5MHz (OSR=16)，其最大訊號對雜訊和失真比在輸入為-6dBFS是59.65 dB，整體功率消耗為39.28mW。

關鍵字

差和調變器；雜訊耦合

並列摘要

In this thesis, a switched-capacitor (SC) double-sampling three-bit sixth-order bandpass delta-sigma modulator with tunable resonators is proposed. It achieves sixth-order noise shaping by using tunable SC resonators and quantization noise coupling, and only three opamps are used so that the overall power consumption is lower compared to that of the conventional architecture. The feed-forward topology can reduce the distortion in the signal path, and efficiently reduce the circuit complexity and physical area, especially when the loop contains a multi-bit quantizer. Besides, the tunable resonator can increase the signal-to-noise and distortion ratio (SNDR) in lower oversampling ratio situation by properly adjusting the resonator frequency. In addition, double-sampled technique provides a good method of increasing the sampling frequency without many efforts and relaxes the performance requirement of the operational amplifier. An active adder opamp is used before the quantizer to avoid any signal attenuation due to parasitics, and any kick-back noise from the quantizer. This adder is also used for quantization noise coupling to provide further noise shaping. Additionally, we present the filter-based data-weighted averaging (DWA) to modify the nonlinearity problem of the digital-to-analog converter generated by capacitor mismatch errors. The design procedure is summarized in the following: First, we use MATLAB and SIMULINK to verify the stability and estimate the performance. Then, Hspice is used for transistor level simulation. The final implementation of the modulator works at 1.5V supply, clock frequency is 40MHz (effective frequency would be 80MHz), and the input center frequency is 20MHz in TSMC 0.18m CMOS 1P6M process. Simulation results reveal that the peak SNDR is 59.65 dB with -6dBFS input for bandwidth 2.5MHz (OSR=16), and power consumption is 39.28mW.

並列關鍵字

delta-sigma modulator ； noise coupling

參考文獻

[1] S.-C. Huang, M.-H. Liao, and C.-S. Hsu, “A low-distortion fourth-order bandpass delta-sigma modulator,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 5383-5386, 2006.

[2] J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electron. Lett., vol. 37, no.12, pp. 737-738, Jun. 2001.

[5] L. Cardelli, L. Fanucci, V. Kempe, F. Mannozzi, and D. Strle, “Tunable bandpass sigma delta modulator using one input parameter,” Electron. Lett., vol. 39, no. 2, pp. 187-189, Jan. 2003.

[7] L. Longo and B.-R. Horng, “A 15 b 30 kHz bandpass sigma-delta modulator,” in Proc. IEEE ISSCC Dig. Tech. Papers, pp. 226-227, Feb. 1993.

[8] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing, Wiley, 1986.

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採用可調式共振器之雙取樣三位元四階帶通雜訊耦合差和調變器設計

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