採用可調式共振器之雙取樣三位元四階帶通差和調變器設計

在本篇論文中，我們提出以前饋式架構為基礎的可調式共振器及主動式加法之雙取樣三位元四階帶通差和調變器。採用前饋式架構能降低輸入訊號失真，在多位元量化器中能明顯的減少電路複雜度並且節省晶片面積。使用可調式共振器，只需調整架構上的參數，來選取最佳的調變器得到規格應用所需的陷波(notch) 頻率,並且僅使用一個運算放大器來實現，能有效降低功率消耗。此外，利用雙取樣技術，不但提高取樣頻率且可舒緩放大器速度上的規格要求。並且在量化器之前使用主動式加法，能避免訊號受寄生效應及突波回授雜訊影響。另外，我們還提出自耦合帶通雜訊整形及排序動態元素匹配架構，並以系統模擬驗證。整體設計流程首先利用MATLAB 及SIMULINK來驗證系統穩定度及評估整體效能。接著利用Hspice作電晶體層級的模擬，最後採用TSMC 0.18m CMOS 1P6M實現電路設計，使用1.5伏電壓，調變器的時脈頻率為40MHz (相當於80MHz的取樣頻率)，輸入中心頻率為20MHz。在頻寬為5MHz (OSR=8)，其最大訊號對雜訊和失真比在輸入為-12dBFS是47.48dB；另外，在頻寬為0.625MHz (OSR=64)，在輸入同樣為-12dBFS是62.42dB，整體功率消耗為46mW。

關鍵字

可調式共振器；雜訊耦合；動態元素匹配；帶通差和調變器；雙取樣

並列摘要

In this thesis, a switched-capacitor (SC) double-sampling three-bit fourth-order bandpass delta-sigma modulator with tunable resonators and active adder opamp based on feed-forward topology is proposed. The feed-forward topology can reduce the distortion in the signal path, and efficiently reduce the circuit complexity and physical area, especially when the loop contains a multi-bit quantizer. The tunable resonator can optimize modulator performance for band of interest by adjusting the resonator frequency with selecting switches, and the resonator just needs one operation amplifier to realize that can reduce the power consumption. Additionally, double-sampled technique provides a good method of increasing the sampling frequency without many efforts and relaxes the performance requirement of the operational amplifier. An active adder opamp is used before the quantizer to avoid any signal attenuation due to parasitics, and any kick-back noise from the quantizer. In addition, we also presented the self-coupling bandpass noise shaping, and sorting algorithm DEM, and they are verified by the system level simulation. The design procedure is summarized in the following: First, we can use MATLAB and SIMULINK to verify the stability and estimate the performance. Then, Hspice is used for transistor level simulation. The final implementation of the modulator works at 1.5V supply and clock frequency is 40MHz (effective frequency would be 80MHz), the input center frequency is 20MHz in TSMC 0.18m CMOS 1P6M process. Simulation results reveal that the peak SNDR is 47.48dB and 62.42dB with -12dBFS input for bandwidth 5MHz (OSR=8) and bandwidth 0.625MHz (OSR=64), respectively, and power consumption is 46mW.

並列關鍵字

tunable resonator ； bandpass delta-sigma modulator ； noise coupling ； double-sampling ； DEM

參考文獻

[2] D. Johns. and K. Martin, Analog integrated circuit design, Wiley, 1997.

[3] J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electron. Lett., vol. 37, no.12, pp. 737-738, Jun. 2001.

[4] S.-C. Huang, M.-H. Liao, and C.-S. Hsu, “A low-distortion fourth-order bandpass delta-sigma modulator,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 5383-5386, 2006.

[6] L. Cardelli, L. Fanucci, V. Kempe, F. Mannozzi, and D. Strle, “Tunable bandpass sigma delta modulator using one input parameter,” Electron. Lett., vol. 39, no. 2, pp. 187-189, Jan. 2003.

[9] L. Longo and B.-R. Horng, “A 15 b 30 kHz bandpass sigma-delta modulator,” in Proc. IEEE ISSCC Dig. Tech. Papers, pp. 226-227, Feb. 1993.

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採用可調式共振器之雙取樣三位元四階帶通差和調變器設計

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